Commit graph

43 commits

Author SHA1 Message Date
Daniel Leung
6d5e0c25a6 xtensa: rename z_xtensa_irq to simple xtensa_irq
This gets rid of the z_ prefix.

Note that z_xt_*() are being used by the HAL so they cannot be
renamed.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Zhang Peng
9dd10c2f3c soc: xtensa: adsp: add support for NXP ADSP for i.MX8ULP
Add support for i.MX8ULP target.

Signed-off-by: Zhang Peng <peng.zhang_8@nxp.com>
2023-12-04 16:41:00 +00:00
Iuliana Prodan
9af6825874 nxp_adsp: linker: Add snippets to linker script
The xtensa/nxp_adsp_imx8m linker script is missing
the necessary include statements for linker snippets.
So we need to add them.

This fixes compile warnings like: orphan section `.unstable_id'
from `modules/chre/lib..__modules__lib__chre__platform__zephyr.a
(version.cc.obj)' being placed in section `.unstable_id'.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2023-11-20 11:13:44 +01:00
Iuliana Prodan
9cac089f8c nxp_adsp: linker: Fix _heap_sentry reference
Add _heap_sentry value to fix build errors for
newlib, like: "undefined reference to `_heap_sentry'"

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2023-11-20 11:13:44 +01:00
Iuliana Prodan
23c49e554a nxp_adsp: linker: Update linker scripts for C++ build
When linking, in crtbegin.o for C++ exception support, we pull in
the .tm_clone_table section.
Update the linker scripts to handle this, otherwise we get a
"warning: orphan section `.tm_clone_table'".

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2023-11-20 11:13:44 +01:00
Iuliana Prodan
24f2d2e136 nxp_adsp: linker: Rename text area variables
Use Zephyr's convention for text region start and end.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2023-11-20 11:13:44 +01:00
Iuliana Prodan
edc0b7f352 board: xtensa: imx8m: Remove unnecessary configs
Remove unnecessary configs.
Some were moved to Kconfig.series from soc/.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2023-11-20 11:13:44 +01:00
Iuliana Prodan
afc3606116 soc: xtensa: imx8m: Remove unused definitions
Remove unused macro definitions.

While here, use Zephyr's convention for
include guard.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2023-11-20 11:13:44 +01:00
Iuliana Prodan
85a1124d5d soc: xtensa: imx8m: Remove unused file
Remove platform.h since is no longer used for SOF.
Move memory.h to include folder and modify the linker
to reflect this.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2023-11-20 11:13:44 +01:00
Laurentiu Mihalcea
707759bd12 soc: xtensa: imx8: Add pinctrl support
This commit introduces support for pinctrl-related operations
on i.MX8QM/QXP.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2023-11-09 18:21:05 +01:00
Laurentiu Mihalcea
eb12bae048 soc: xtensa: imx8: Configuration cleanup
As the name suggests, this commit attempts to cleanup some
of the configurations for the i.MX8 series. This cleanup
consists of either relocating the configuration or removing
unnecessary configurations.

As a rule of thumb, SoC-specific configurations have been moved
to Kconfig.series. If the configuration is by default 'y' and
needs to be set to 'n' or it has a numeric value then it has
been moved to Kconfig.defconfig.series. Configurations that
are default 'n' and were also explicitly set to 'n' have been
removed. Also, enabling logging has been moved to the board
level to avoid having to force all boards based on the same
SoC to enable logging.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2023-11-09 18:21:05 +01:00
Laurentiu Mihalcea
ad7e858938 soc: xtensa: imx8: memory.h: Cleanup
This commit attempts to clean the memory.h header by doing
the following changes:
	1) Change the include guard to the standard
	ZEPHYR_....
	2) Remove unused macro definitions.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2023-11-09 18:21:05 +01:00
Laurentiu Mihalcea
f29d6edece soc: xtensa: imx8: Remove include/soc directory
Since platform.h is a SOF-specific header that's no
longer used there's no point in keeping the include/soc directory.
As such, move memory.h to include/ and modify the linker script
to reflect this location change.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2023-11-09 18:21:05 +01:00
Laurentiu Mihalcea
a0ecc05cdf soc: xtensa: imx8: Split generic i.MX8 SoC into i.MX8QXP and i.MX8QM
This commit attempts to split the generic i.MX8 SoC into its
QXP and QM variants. As things are now, the i.MX8 SoC doesn't
have any NXP HAL files to back it up. As a consequence, the
native Zephyr drivers cannot be used.

To solve this issue, the generic i.MX8 has been split into
i.MX8QXP and i.MX8QM, each of them having different NXP HAL
files.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2023-11-09 18:21:05 +01:00
Torsten Rasmussen
ba7e6fa69f cmake: cleanup and simplify the standard include logic in Zephyr
Several paths are checked for existence before added as global Zephyr
include path.

The existence check was needed because some tooling emit warnings on
non-existing paths.

Only few SoCs are using those pre-defined paths, yet this code runs
for all SoCs. The principle originates back from Kbuild days, and with
CMake it's more common and generally more visible to let the CMake code
defining libraries to specify include paths.

Furthermore it appears that several SoC implementation following the
<soc-path>/include was unaware that the path would be automatically
added as include path, cause they contain lines like:
    zephyr_library_include_directories(include)

Remove pre-defineds path except the `<SOC_PATH>` path, which is
guaranteed to exists.
This simplifies the CMake logic in the top-level Zephyr CMakeLists.txt
file.

This cleanup further prepares for future work where SoCs need not to
be organised under architectures which is important for multi-arch SoCs.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2023-11-06 18:57:30 -05:00
Torsten Rasmussen
4b02bbc329 cmake: xtensa: update xtensa SoC to use SOC_LINKER_SCRIPT variable
This commit updates all xtensa SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2023-11-03 11:01:23 +01:00
Mike J. Chen
385ceb7145 soc: xtensa: nxp_adsp: rt595: move .noinit
Mark .noinit section as NOLOAD and move it
next to the other NOLOAD sections. This way
it is removed from a generated image that is
embedded in the rt595 app image.

Signed-off-by: Mike J. Chen <mjchen@google.com>
2023-11-01 11:19:02 +00:00
Daniel Leung
1fac5ed2a6 soc: xtensa/nxp_adsp: put guard in Kconfig.defconfig
This adds a if CONFIG_SOC_FAMILY_NXP_ADSP guard in
Kconfig.defconfig for nxp_adsp. Or else all of its default
get applied everywhere. For example, qemu_xtensa fails
kernel.logging.message_capture tests because
CONFIG_TEST_LOGGING_DEFAULTS is disabled in
nxp_adsp/Kconfig.defconfig which should not have applied
to qemu_xtensa at all. So put a guard in there.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-10-26 19:16:53 -04:00
Dmitry Lukyantsev
357d6cec45 boards: Add support for the NXP MIMXRT595 DSP core
Add board and soc files for the NXP MIMXRT595 DSP core.

Signed-off-by: Dmitry Lukyantsev <dmitrylu@google.com>
2023-10-25 09:55:10 -04:00
Dmitry Lukyantsev
0ae68a3857 soc: nxp_adsp: Refactor imx8/imx8m Kconfig
In preparation for RT500 ADSP enablement, consolidate common Xtensa
configuration parameters in top level Kconfig.defconfig.

Signed-off-by: Dmitry Lukyantsev <dmitrylu@google.com>
2023-10-25 09:55:10 -04:00
Iuliana Prodan
1295283a8a soc: xtensa: nxp: add resource_table section in linker script
Add resource_table section in linker script for nxp_adsp_imx8m
for inter-process communication.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2023-07-26 14:33:36 +02:00
Marc Herbert
35e8e6fa03 soc/xtensa/nxp_adsp/CMakeLists.txt: use new WEST_SIGN_OPTS variable
Align `soc/nxp_adsp` with new `WEST_SIGN_OPTS` option added to
`soc/intel_adsp` by recent commit d98a7c2f8d ("soc: xtensa: cmake: add
new WEST_SIGN_OPTS variable").

This allows per-board rimage customization at the CMake level. Example
in `zephyr/boards/xtensa/nxp_adsp_NEWBOARD/board.cmake`:

  set(WEST_SIGN_OPTS -- -c rimage/config/special.toml)

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-07-13 14:19:26 +02:00
Iuliana Prodan
dc49a314fd west: sign.py: fix sign when CONFIG_KERNEL_BIN_NAME is used
This fixes the following build error:
```
zephyr/zephyr.elf', needed by 'zephyr/zephyr.ri', missing and no known
rule to make it
```
This appears when CONFIG_KERNEL_BIN_NAME is used.

Therefore, do not use zephyr.elf since some samples might be called
based on CONFIG_KERNEL_BIN_NAME.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2023-07-10 09:29:33 +02:00
Anas Nashif
c62e55973b intel_adsp: remove deprecated cache macros
SOC_DCACHE_FLUSH and SOC_DCACHE_INVALIDATE are not being used anywhere.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-06-23 11:14:08 -04:00
Laurentiu Mihalcea
58d1c6146c soc: xtensa: nxp_adsp: Enable cache management API for NXP SoCs
Thanks to PR [1] which introduces support for cache management
operations on xtensa architecture NXP SoCs can now use the
Zephyr native cache management API.

This commit enables some configurations that will allow us
to use the native Zephyr cache management API.

[1]: https://github.com/zephyrproject-rtos/zephyr/pull/50136

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2023-05-17 18:34:24 -04:00
Marc Herbert
5ae7bd84d3 soc: xtensa: nxp: invoke west sign at west build time
This aligns `soc/xtensa/nxp_adsp/` with commit
fad2da39aa ("intel_adsp: move `west sign` from `west flash` to earlier
`west build`")

The --if-tool-available option preserves backwards-compatibility:
nothing happens if rimage is not found.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-05-16 12:08:43 +02:00
Iuliana Prodan
b2f1f64f57 boards: xtensa: nxp_adsp_imx8m: Add UART support for the ADSP from i.MX8MP
Enable UART on the DSP from the i.MX8MP target:
- add corresponding nodes in dtsi and dts;
- create a dts overlay for uart;
- add a config fragment for uart and console configuration.

So, in order to compile an application and enable UART
a user must run west build using DTC_OVERLAY_FILE and CONF_FILE.

Here's an example for hello_world:
west build -p always -b nxp_adsp_imx8m samples/hello_world/
-DDTC_OVERLAY_FILE="boards/xtensa/nxp_adsp_imx8m/
nxp_adsp_imx8m_uart.overlay" -DCONF_FILE="boards/xtensa/nxp_adsp_imx8m/
nxp_adsp_imx8m_uart.conf"

For other applications, like SOF, where we don't need UART, we simply run:
west build -p always -b nxp_adsp_imx8m ../modules/audio/sof/ --
-DTOOLCHAIN=/opt/zephyr-sdk-0.15.2/xtensa-nxp_imx8m_adsp_zephyr-elf/
bin/xtensa-nxp_imx8m_adsp_zephyr-elf -DINIT_CONFIG=imx8m_defconfig

The nxp_adsp_imx8m is using the nxp_imx_iuart driver.
For now, is used in poll mode.
Next step is to enable the interrupt controller in
DSP and use the interrupt driver UART.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2023-05-08 13:06:12 -05:00
Iuliana Prodan
98bc2d8a40 soc: xtensa: nxp_adsp: imx8m: rename soc
Rename soc to mimx8ml8 to link this board to the
MIMX8ML8 device from nxp_hal/mcux/mcux-sdk/.

We need this in order to use the drivers from mcux-sdk.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2023-05-08 13:06:12 -05:00
Paul Olaru
fa5117225a nxp_adsp: Do not use xtensa hal with xcc-clang
Do not use XTENSA_HAL when building with xt-clang, instead use the HAL
that is provided by the toolchain, similarly to xt-xcc.

Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
2023-05-02 11:12:52 -05:00
Anas Nashif
6388f5f106 xtensa: use sys_cache API instead of custom interfaces
Use sys_cache instead of custom and internal APIs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-04-26 07:31:22 -04:00
Flavio Ceolin
e3aac24821 xtensa: linker: Use zephyr's convention for rodata
Zephyr maps start/end of rodata section with variables
using __rodata_region namespace. The exception was Xtensa.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-11-17 15:44:48 +09:00
Ederson de Souza
d7f46136e0 soc/xtensa: Use standard __data_start/__data_end markers
Xtensa is the odd one out by using _data_start/_data_end instead. Using
the Zephyr standard helps avoid ifdefs for common code, like tests.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-11-03 10:25:07 +01:00
Gerard Marull-Paretas
edfcd0ab51 soc: xtensa: nxp_adsp: add missing xtensa irq.h include
The file uses architecture specific IRQ calls without including
appropriate headers.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-11 18:05:17 +02:00
Gerard Marull-Paretas
d342e4c4c1 linker: update files with <zephyr/...> include prefix
Linker files were not migrated with the new <zephyr/...> prefix.  Note
that the conversion has been scripted, refer to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 12:45:29 -04:00
Gerard Marull-Paretas
0e69129fb3 soc: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all soc code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:57:59 +02:00
Daniel Baluta
c3c026e03c arch/xtensa: adsp: Rename module_init section
.module_init sections is used to keep all components constructor
functions.

Zephyr uses -ffunction-sections option which will create a section for
each function. Unfortunately, this creates a section named .module_init
for the function module_init() used to initialize the processing module
generic layer.

Thus, places module_init() in the constructor area named .module_init
which is wrong.

To avoid this we rename .module_init section for constructors to
.initcall.

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2022-04-26 15:54:46 -04:00
Gerard Marull-Paretas
c925b5991a include: remove unnecessary autoconf.h includes
The autoconf.h header is not required because the definitions present in
the file are exposed using the compiler `-imacros` flag.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-04-05 11:18:20 +02:00
Daniel Baluta
feffe639a3 soc: xtensa: adsp: Fix i.MX8 hw_cycles_per_sec definition
Acorrding to RM, HIFI4 DSP default configured frequency is:
	- 666Mhz for i.MX8
	- 800Mhz for i.MX8M

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
2022-03-02 10:08:52 -08:00
Andy Ross
c174ade4a1 arch/xtensa: Rework irq_offload: automatic config, SMP-safe
The Xtensa implementation of arch_irq_offload() required that the user
select the correct interrupt manually, and would race with itself if
invoked from separate CPUs (it was saved here by the main
irq_offload() function which has a semaphore to serialize access).

Use the new gen_zsr.py script to automatically detect the highest
available software interrupt, and keep a per-CPU set of
callback/parameter pointers.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2022-02-21 22:10:03 -05:00
Marc Herbert
5d4e08bb9f soc: xtensa: cavs-link.ld: add *(.trace_ctx) sections
Copy/paste/diverge struck again; I should have known better.

Fixes very recent and incomplete commit 9a1c5ec78e ("soc/intel_adsp:
cavs-link.ld: add *(.trace_ctx) sections"), see that commit for details.

Part of the fix for thesofproject/sof/issues/5032

This commit does not change `soc/xtensa/sample_controller/linker.ld`

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2021-12-22 17:47:21 -06:00
Iuliana Prodan
8bbb11d6a1 soc: xtensa: adsp: add support for NXP ADSP for i.MX8MP
Add support for i.MX8MP target.
This has a 1 Xtensa HiFi4 core, with 64 KB TCM,
256KB OCRAM, 8MB SDRAM and 1 SAI as audio interface.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2021-10-20 19:08:50 -04:00
Iuliana Prodan
f9810ccbe1 arch: xtensa: modify asm for interrupt sections
For IMX, for timer interrupt, the interrupt handler
was not the correct one executed and that’s because
the handlers were not at the expected address.
For IMX the size constraint of the interrupt vector
table entry is 0x1C bytes of code, less than usual.

I've added a small indirection to bypass this size
constraint and moved the default handlers to the end
of vector table, renaming them to
_Level\LVL\()VectorHelper.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2021-08-28 23:27:02 -04:00
Iuliana Prodan
9dcd562608 soc: xtensa: adsp: add support for NXP ADSP
Add a common part for all i.MX boards.

Add support for i.MX8, which represents i.MX8QM.
This has a 1 Xtensa HiFi4 core, with 64 KB TCM,
448 KB OCRAM, 8MB SDRAM and 1 ESAI, 1 SAI as
audio interfaces.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2021-08-28 23:27:02 -04:00