Commit graph

59666 commits

Author SHA1 Message Date
Julien Massot
39e03d0c3f dts: arm: r8a77951: add pin-controller node
Pin controller address is the same for all member of the
GEN3 SoC Series, but pinmux configuration is SoC specific.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2022-01-17 21:00:58 +01:00
Julien Massot
b06862ca11 dts: bindings: pinctrl: add Renesas R-Car Pinmux
Renesas R-Car series contains a PFC (Pin Function Controller).
This module consists of registers for selecting the function of
the multiplexed pins and controls the pull-up resistor on each pin.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
2022-01-17 21:00:58 +01:00
Piotr Pryga
ab32c06275 samples: Bluetooth: df: Fix possible stack overflow issue
Host receive thread has small default stack size.
Attempt to convert data from binany to string requires
large array. Allocation of such array on stack could
cause stack overflow.

To limit the scope of the array and avoid stack overflow
the array is changed to be static local variable in a function.

Also the array has been prepared to accept max advertising
data sieze of 1650 bytes.

Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
2022-01-17 12:54:10 -05:00
Lukasz Majewski
c9902412e6 fs: Extend the littlefs code to support block devices
Up till now the littlefs only has been supporting the flash medium in
Zephyr.

This change provides code to also use littlefs stored on the block
devices - like SD card (accessed via SPI).

When FS_LITTLEFS_BLK_DEV Kconfig option is defined, the support for
using littlefs on block devices is enabled.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2022-01-17 12:53:43 -05:00
Lukasz Majewski
6fa771f2d0 fs: littlefs: Rename *area (struct flash_area*) to *backend void pointer
The struct flash_area *area pointer has been renamed to void *backend
pointer.

This change is enabling further rework of the littlefs subsystem to work
with other backend devices (like block ones - i.e. SD card).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2022-01-17 12:53:43 -05:00
Gerard Marull-Paretas
d2538475c6 doc: fix PDF build issue due to extlink references
LaTeX code generated by Sphinx causes problems when using extlinks in
references. Mitigate the problem by just using the extlink role
directly.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-17 12:48:43 -05:00
Henrik Brix Andersen
2c0e0a74af doc: use extlink for github issue links
Use extlink for GitHub issue links in documentation.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-01-17 12:48:43 -05:00
Trond Einar Snekvik
eadf04af82 Bluetooth: Mesh: Return a boolean from subnet_find callback
bt_mesh_subnet_find calls a callback for every subnet, and returns the
subnet that got a non-zero return code from the callback. As pointed out
in #41693, the callback should return a boolean, not an int.

Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
2022-01-17 11:52:57 -05:00
Tim Lin
013bc73e40 ITE: cleanup: drivers/bbram: correct the default configuration format
1. Rename DT_COMPAT_ST_BBRAM_IT8XXX2 to COMAPT_ITE_IT8XXX2_BBRAM
2. The default configuration "$( )" should be a parentheses instead
   of curly brackets. The BBRAM for it8xxx2 can be driven after
   correcting.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-01-17 11:52:13 -05:00
Tim Lin
95ba8e3fe4 ITE: drivers/bbram: add magic number to compare in initial
BBRAM content should be cleared when boot from cutoff. Compare magic
number to decide whether to clear entire BBRAM.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2022-01-17 11:52:13 -05:00
Maureen Helm
e0cb96c4e3 drivers: flash: Refactor drivers to use shared init priority
Refactors all of the on-chip flash drivers to use a shared driver class
initialization priority configuration, CONFIG_FLASH_INIT_PRIORITY, to
allow configuring flash drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.

The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers.

Driver-specific options for SPI-based flash drivers are left intact
because they need to be initialized at a different priority than on-chip
flash drivers.

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2022-01-17 11:51:09 -05:00
Jedrzej Ciupis
81ea529960 drivers: ieee802154: extend support for nRF53
This commit updates the ieee802154 driver to match the current feature
set of the nRF 802.15.4 radio driver for nRF53 SoCs.

Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
2022-01-17 11:50:38 -05:00
Alexander Wachter
41643b0fac drivers: can: stm32fd: fix type of clock rate
the rate_tmp varaiable was int, but should be const uint32_t.

Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
2022-01-17 11:50:06 -05:00
Przemyslaw Bida
21200b54f7 boards: Fix arduino_nano_33_ble PCB initialization problem.
The board_internal_sensors_init function was called erlier than the GPIO
driver was initialized. This commit fixes the issue.

Signed-off-by: Przemyslaw Bida <przemyslaw.bida@nordicsemi.no>
2022-01-17 11:48:56 -05:00
Alexander Mihajlovic
cfce5afcd9 drivers: adc: stm32: Clear ADRDY before waiting
Clear ADRDY before enabling ADC to ensure the subsequent
wait for ADRDY does not stop prematurely in case ADRDY
was already set.

The "ADC on-off control" sections of the following reference manuals
were consulted. That gives at least one instance per series affected
by this change, even if not every affected MCU is covered.

- RM0438 (STM32L552xx and STM32L562xx)
- RM0351 (STM32L47xxx, STM32L48xxx, STM32L49xxx and STM32L4Axxx)
- RM0434 (STM32WB55xx and STM32WB35xx)
- RM0454 (STM32G0x0)
- RM0440 (STM32G4 Series)
- RM0399 (STM32H745/755 and STM32H747/757)
- RM0433 (STM32H742, STM32H743/753 and STM32H750)
- RM0453 (STM32WL5x)

Signed-off-by: Alexander Mihajlovic <a@abxy.se>
2022-01-17 11:48:30 -05:00
Alexander Mihajlovic
e521c7d49e drivers: adc: stm32: Add function to enable ADC consistently
Use a wrapper for LL_ADC_Enable that also waits for ADRDY if required
by the SoC to make sure it's properly enabled everywhere this is done.

Signed-off-by: Alexander Mihajlovic <a@abxy.se>
2022-01-17 11:48:30 -05:00
Alexander Mihajlovic
1cd1f41d3a tests: drivers: adc: Add support for nucleo_wl55jc
Add support for nucleo_wl55jc board to adc_api test.

Signed-off-by: Alexander Mihajlovic <a@abxy.se>
2022-01-17 11:48:30 -05:00
Alexander Mihajlovic
b9aca25206 samples: adc: Add nucleo_wl55jc support
Add support for nucleo_wl55jc board to adc driver sample.

Signed-off-by: Alexander Mihajlovic <a@abxy.se>
2022-01-17 11:48:30 -05:00
Alexander Mihajlovic
44601330b0 boards: nucleo_wl55jc: Add support for ADC samples
Add pinmux for ADC on Arduino pin A0 and enable ADC1.

Signed-off-by: Alexander Mihajlovic <a@abxy.se>
2022-01-17 11:48:30 -05:00
Henrik Brix Andersen
d5fb436f73 drivers: can: shell: catch up with recent CAN API naming changes
Rename CAN RX filter shell commands to catch up with the CAN API naming
changes in 8af4bb722d.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-01-17 11:48:02 -05:00
Henrik Brix Andersen
dc7903c0dc tests: drivers: can: stm32: filter out boards without st,stm32-can
Filter out boards without st,stm32-can compatibles enabled in their
devicetree in the stm32-specific CAN driver test.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-01-17 11:47:28 -05:00
Henrik Brix Andersen
71525b9c21 dts: bindings: can: remove can-device.yaml binding
Remove the unused base binding for CAN bus devices (as in devices
present on a CAN bus). This binding should have been removed in
2269408572

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-01-17 11:46:58 -05:00
Antony Pavlov
00ba635d58 boards: arm: add initial support for OLIMEX STM32-H405 board
The board features a STM32F405RGT6 MCU.

The code is based on boards/arm/olimex_stm32_p405 and
boards/arm/olimex_stm32_h103.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2022-01-17 11:46:32 -05:00
Francois Ramu
ff34965a0a samples: drivers led strip ws2812 overlay for stm32 nucleo
The spi node of the led_ws2812 now includes the frame format
as defined by the dts bindings spi-device.yaml
SPI_FRAME_FORMAT_TI is selected with overlay for target boards.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-01-17 11:46:14 -05:00
Francois Ramu
d65a74e2dd drivers: spi: stm32 spi drivers supports the frame format
the stm32 spi drivers now takes the DTS frame_format property
from the include/ drivers/spi.h
It will be possible to select the Motorola (default)
or TI from the DTS entry of the device,
when soc supports it, else a run time error is raised.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-01-17 11:46:14 -05:00
Manojkumar Subramaniam
0757678514 tests: drivers: STM32: Enabling ADC tests for nucleo_h7a3zi_q
This commit enables test_adc to build and run for this new board

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Manojkumar Subramaniam
4c54e23377 samples: drivers: nucleo_h7a3zi_q: Configuring ADC sample application
I tested ADC sample on the board mentioned above
0v = 0
3.3v = 4095

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Manojkumar Subramaniam
c9da36685a boards: nucleo h7a3zi-q: enable SMPS
SMPS supply is default for this board

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Manojkumar Subramaniam
fc79380dc7 boards: Add support for nucleo_h7a3zi_q
Introduce this board, rcc config: the SoC uses slightly different
domain naming, eg: `cdppre` is equivalent to `d1ppre`
D1 = CD
D2 = CD<..>2
D3 = SRD

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Manojkumar Subramaniam
ae0ce3a2b9 drivers: clock_control: stm32h7: Support SoC STM32H7A3XX / STM32H7A3XX-Q
clock requirement

Introduce a new group of clock setting to fit in this series of SoC

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Manojkumar Subramaniam
bd9415e6bf soc: arm: stm32h7: kconfig workaround to handle SoC H7A3XX-Q P/N
Set the correct soc string so that the correct CMSIS file
is being utilised.

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Manojkumar Subramaniam
881407be6e soc: arm: stm32h7: add stm32h7a3xxq
The Q variant is the same as non-Q, except the Q has SMPS built-in.
This symbol addition is to have the correct
SOC definition ("STM32H7A3XXQ")

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Manojkumar Subramaniam
a268d8b07e soc: arm: stm32h7: add stm32h7a3xx support
Basic kconfig config.

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Manojkumar Subramaniam
ceaa303527 dts: arm: st: h7a3: add support for stm32h7a3
Introduce device tree support for this family of SoC

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2022-01-17 11:45:21 -05:00
Ruibin Chang
336d0f67b3 ITE drivers/kscan: support tests/driver/kscan/kscan_api
Add kscan0 to support tests/driver/kscan/kscan_api.

When running the tests code on it8xxx2_evb, it shows fatal
error: IRQ is enabled. We find that once polling_task() is
created and executed, the KSI interrupt will be enabled and
before we call irq_connect_dynamic(), so we switch both
function sequence.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2022-01-17 11:44:05 -05:00
Anders Storrø
8d9735824a Bluetooth: Mesh: GATT proxy enable fix for ext adv
Adds fix so that a node running with extended adveriser is able to
enable GATT proxy correctly. This fixes a corner case issue  where a
device with no other ongoing message sending is unable to advertise
the GATT proxy through
bt_mesh_gatt_proxy_set(BT_MESH_FEATURE_ENABLED) .

Signed-off-by: Anders Storrø <anders.storro@nordicsemi.no>
2022-01-17 11:43:39 -05:00
Gerard Marull-Paretas
36515919b5 doc: fix kconfig usage issues
- Fix some syntax errors, e.g. :c:kconfig:`...`
- Remove references to missing symbols (replaced with literals)

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-17 11:42:53 -05:00
Jordan Yates
bb00120e8b tests: drivers: adc: test dummy ADC driver
Add a testcase for compiling the dummy `vnd,adc` driver.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2022-01-17 08:13:41 -05:00
Jordan Yates
8173277cc1 drivers: adc: test driver
Add a dummy driver for the `vnd,adc` compatible to allow compilation of
drivers utilising an ADC when running "build_all" tests.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2022-01-17 08:13:41 -05:00
Daniel Leung
44462723f5 timer: hpet: make legacy interrupt routing optional
On some platforms, HPET is not wired to trigger IRQ 2.
This would make HPET non-functional if the legacy
interrupt routing bit is set in the global config
register. This adds a DTS flag so the driver won't
set the bit to enable legacy interrupt.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-14 14:46:21 -05:00
HaiLong Yang
1d3c710eaf samples: eeprom: add gd32f450i_eval board
Add gd32f450i_eval board with AT2402C eeprom.

Signed-off-by: HaiLong Yang <cameledyang@pm.me>
2022-01-14 10:42:24 -06:00
HaiLong Yang
4b386940b8 boards: arm: gd32f450i_eval: add i2c0 interface
Add i2c0 interface to gd32f450i_eval board.

Signed-off-by: HaiLong Yang <cameledyang@pm.me>
2022-01-14 10:42:24 -06:00
HaiLong Yang
5a7aeb9439 drivers: i2c: introduce GD32 I2C driver
Add an interrupt driven i2c driver for gd32 i2c peripheral.

The transmit and reception method refer from GD32 SoCs user manual.
Particularly, reception method choose the solution B.

There have some wait for state ready logic in the driver. It cause by
i2c device internal state change slower than i2c driver.

Signed-off-by: HaiLong Yang <cameledyang@pm.me>
2022-01-14 10:42:24 -06:00
HaiLong Yang
48af32d3d8 dts: i2c: introduce gd32 i2c interface
Add gd32 i2c interface support.

Signed-off-by: HaiLong Yang <cameledyang@pm.me>
2022-01-14 10:42:24 -06:00
HaiLong Yang
76968d9786 manifest: upgrade hal_gigadevice
upgrade hal_gigadevice to get i2c clock frequency boundary definition.

Signed-off-by: HaiLong Yang <cameledyang@pm.me>
2022-01-14 10:42:24 -06:00
Francois Ramu
f6c0362664 tests: drivers: spi loopback remove conf for most of the stm32 boards
The testcase is including a generic configuration conf
for the stm32 target boards when running the SPI loopback in
interrupt and DMA mode. Thus, the board specific conf file is useless.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-01-14 10:09:00 -06:00
Francois Ramu
a7d2b2a9f9 tests: drivers: spi loopback testcase on spi2 for stm32 boards
Overwrites the overlay for testing the SPI2 when running on
nucleo_f302r8 and 96b_carbon targets.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-01-14 10:09:00 -06:00
Francois Ramu
a3680c1b00 tests: drivers: spi loopback testcase yaml for stm32 dma
This commit adds two stm32 config to execute the testcase
when the SPI is using interrupt mode for transfer.
when the SPI is using DMA for transfer (not Interrupt nor ASYNC mode).
to run the on some specific (listed) stm32 boards on SPI instance.
Note the hw fixture (physical connection on the board)

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-01-14 10:09:00 -06:00
Filipe Rinaldi
a35848b7d7 boards: fvp_baser_aemv8r: fix UART enablement
Fix the interrupt setting in the fvp_baser_aemv8r dts:
- The correct interrupt number is 5, not 0.
- The interrupt priority and type are swapped.

This patch also enables interrupt driven mode for this platform as this
is the ideal setting for a Fast Models based platform.

Issue-ID: SCM-4037
Signed-off-by: Filipe Rinaldi <filipe.rinaldi@arm.com>
Change-Id: Ic4815f5afe4c9df9d8fe373d47d2773d64087c96
2022-01-14 10:00:54 -06:00
TOKITA Hiroshi
c72b75fc45 boards: riscv: longan_nano: Add LED and button configuration
Add configuration to support onboard LED and button.

- LED_R: PC13 (active low/output)
- LED_G: PA1  (active low/output)
- LED_B: PA2  (active low/output)
- BOOT0: PA8  (active high/input)

And enable timer1 to control LED_G and LED_B with PWM.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2022-01-14 09:59:35 -06:00