Some toolchain variants come with no clang support, so do not assume
clang by default and enable this using the enviornment variable
XCC_USE_CLANG.
export XCC_USE_CLANG=1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
There is a race between k_sem_take() and k_object_access_grant() so it
is possible (especially when testing SMP) that the thread tries to take
the semaphore before the originating thread has had the chance to
grant it permission.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Use kinetis SIM clock divider options set in device tree
instead of hardcoded values.
The kl25z device tree did not previously define a MCG node.
This has now been added with the general "nxp,kinetis-mcg"
binding.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Use kinetis SIM clock divider options set in device tree
instead of kconfig.
The kv5x device tree originally used the undefined
"nxp,kv58-mcg" binding for the MCG node. This has been
replaced by the general "nxp,kinetis-mcg" binding.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Use kinetis SIM clock divider options set in device tree
instead of kconfig.
Both the kw40z and kw41z device tree originally used an
undefined "nxp,kw41z-mcg" binding for the MCG node.
This has been replaced with the general "nxp,kinetis-mcg"
binding instead.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
SYSCLK_DEFAULT_IOSC_HZ and BUSCLK_DEFAULT_IOSC_HZ are
not used anywhere in the tree and can be removed
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Add MCGOUTCLK define to kinetis_mcg.h to make it possible to
use \`<&mcg KINETIS_MCG_OUT_CLK>\` in device tree.
Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
Add testcase for deadline_set. Test the situation when threads are
in unqueued state. The k_thread_deadline_set() call should not make
these threads run before there delay time pass.
Signed-off-by: Ying ming <mingx.ying@intel.com>
The test granted access to the user work queue stack from the user
work thread; this was done by k_work_user_queue_start() so was
unnecessary. Document why it's ok to grant other access after the
work thread was started.
Fix a race condition where the non-work user thread might have started
before it was given access to the resources it needs.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The code here was written to "get out of the way just long enough for
the trivial context switch and callback to execute". But on a machine
with 50 kHz ticks, that's not reliably enough time and this was
failing spuriously. Which would have been a reasonably forgivable
mistake to make had I not written this code with this very machine in
mind...
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These tests would pass pointers to data on their own stacks to other
threads, which is forbidden when CONFIG_KERNEL_COHERENCE (because
stack memory isn't cache-coherent). Make the variables static.
Also, queue had two sleeps of 2 ticks (having been written in an era
where that meant "20-30ms"), and on a device with a 50 kHz tick rate
that's not very much time at all. It would sometimes fail spuriously
because the spawned threads didn't consume the queue entries in time.
How about 10ms of real time instead?
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When we reach this code in interrupt context, our upper GPRs contain a
cross-stack call that may still include some registers from the
interrupted thread. Those need to go out to memory before we can do
our cache coherence dance here.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Putting spinlocks (or things containing them) onto the stack is a
KERNEL_COHERENCE violation. This doesn't need to be there so just
make it static.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Both new thread creation and context switch had the same mistake in
cache management: the bottom of the stack (the "unused" region between
the lower memory bound and the live stack pointer) needs to be
invalidated before we switch, because otherwise any dirty lines we
might have left over can get flushed out on top of the same thread on
another CPU that is putting live data there.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The Xtensa L1 cache layer has straightforward semantics accessible via
single-instructions that operate on cache lines via physical
addresses. These are very amenable to inlining.
Unfortunately the Xtensa HAL layer requires function calls to do this,
leading to significant code waste at the calling site, an extra frame
on the stack and needless runtime instructions for situations where
the call is over a constant region that could elide the loop. This is
made even worse because the HAL library is not built with
-ffunction-sections, so pulling in even one of these tiny cache
functions has the effect of importing a 1500-byte object file into the
link!
Add our own tiny cache layer to include/arch/xtensa/cache.h and use
that instead.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Back when I started work on this stuff, I had a set of notes on
register windows that slowly evolved into something that looks like
formal documentation. There really isn't any overview-style
documentation of this stuff on the public internet, so it couldn't
hurt to commit it here for posterity.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Instead of passing the crt1 _start function as the entry code for
auxiliary CPUs, use a tiny assembly stub instead which can avoid the
runtime testing needed to skip the work in _start. All the crt1 code
was doing was clearing BSS (which must not happen on a second CPU) and
setting the stack pointer (which is wrong on the second CPU).
This allows us to clean out the SMP code in crt1.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Zephyr's normal architecture is to do all initialization in the
interrupt stacks. The CAVS code was traditionally written to start
the stack at the end of HP-SRAM, where it has no protection against
overlap with other uses (e.g. MP startup used the same region for
stacks and saw cache collisions, and the SOF heap lives in this area
too). Put it where Zephyr expects and we'll have fewer surprises.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The kernel passes the CPU's interrupt stack expected that it will
start on that, so do it. Pass the initial stack pointer from the SOC
layer in the variable "z_mp_stack_top" and set it in the assembly
startup before calling z_mp_entry().
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There's no need to muck with the cache directly as long as we're
careful about addressing the shared start record through an uncached
volatile pointer.
Correct a theoretical bug with the initial cache invalidate on the
second CPU which was actually doing a flush (and thus potentially
pushing things the boot ROM wrote into RAM now owned by the OS).
Optimize memory layout a bit when using KERNEL_COHERENCE; we don't
need a full cache line for the start record there as it's already in
uncached memory.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The multiprocessor entry code here had some bits that look to have
been copied from esp32, including a clumsy stack switch that's needed
there. But it wasn't actually switching the stack at all, which on
this device is pointed at the top of HP-SRAM and can stay there until
the second CPU swaps away into a real thread (this will need to change
once we support >2 CPUS though).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The trace output layer was using this transformation already, make it
an official API. There are other places doing similar logic that can
benefit.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This whole file is written to assume XEA2, so there's no value to
using an abstraction call here. Write to the RSIL instruction
directly.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The xtensa atomics layer was written with hand-coded assembly that had
to be called as functions. That's needlessly slow, given that the low
level primitives are a two-instruction sequence. Ideally the compiler
should see this as an inline to permit it to better optimize around
the needed barriers.
There was also a bug with the atomic_cas function, which had a loop
internally instead of returning the old value synchronously on a
failed swap. That's benign right now because our existing spin lock
does nothing but retry it in a tight loop anyway, but it's incorrect
per spec and would have caused a contention hang with more elaborate
algorithms (for example a spinlock with backoff semantics).
Remove the old implementation and replace with a much smaller inline C
one based on just two assembly primitives.
This patch also contains a little bit of refactoring to address the
scheme has been split out into a separate header for each, and the
ATOMIC_OPERATIONS_CUSTOM kconfig has been renamed to
ATOMIC_OPERATIONS_ARCH to better capture what it means.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There was a bunch of dead historical cruft floating around in the
arch/xtensa tree, left over from older code versions. It's time to do
a cleanup pass. This is entirely refactoring and size optimization,
no behavior changes on any in-tree devices should be present.
Among the more notable changes:
+ xtensa_context.h offered an elaborate API to deal with a stack frame
and context layout that we no longer use.
+ xtensa_rtos.h was entirely dead code
+ xtensa_timer.h was a parallel abstraction layer implementing in the
architecture layer what we're already doing in our timer driver.
+ The architecture thread structs (_callee_saved and _thread_arch)
aren't used by current code, and had dead fields that were removed.
Unfortunately for standards compliance and C++ compatibility it's
not possible to leave an empty struct here, so they have a single
byte field.
+ xtensa_api.h was really just some interrupt management inlines used
by irq.h, so fold that code into the outer header.
+ Remove the stale assembly offsets. This architecture doesn't use
that facility.
All told, more than a thousand lines have been removed. Not bad.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Commit 6b84ab3830 ("kernel/sched: Adjust locking in z_swap()") moved
the call to arch_cohere_stacks() out of the scheduler lock while doing
some reorgnizing. On further reflection, this is incorrect. When
done outside the lock, the two arch_cohere_stacks() calls will race
against each other.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
I have not had time to work with USB recently, so removing myself from
MAINTAINERS and CODEOWNERS for the USB subsystem.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Coverity analysis reported following cases with side effect in assertion
(ASSERT_SIDE_EFFECT):
CID: 219574
CID: 219644
CID: 219659
Avoid issue by loading volatiles to local variables before assertion.
Fixes: #33079Fixes: #33042Fixes: #33030
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Serial Wire JTAG configuration option is made available
under condition that SPI_3 was not enabled on SOC_STM32F103XE.
Besides being obsolete there are various other potential conflicts
with other periphals, and it is not possible to explicit them all.
To make it more coherent remove such condition, assume that user
needs to take care of such pin conflict and express SWJ as having
precedence over peripheral devices pin configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
MCUboot recently gives possibility to signal its state
using led.
For leverage this feature need to provide proper alias
for the led gpio pin.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Mcuboot was updated to the version synchronized with
the upstream 5b7ed6a which introduces:
- Added LED support for signaling enter to the serial recovery mode
- Added boot delay/debonuce of serial detect pin.
- Fixed compilation warnings with ZEPHYR_LOG_MODE_MINIMAL
- Added optional check which prevents attempting to boot image that
has been build for different ROM address than a slot it currently
resides in. Check is enabled if image was signed with
IMAGE_F_ROM_FIXED flag.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Sometimes it is hard to tell which instance of a thread is which
in the printed list, based solely on the name (if present) and
the k_thread pointer, so also print the thread entry fn pointer.
Signed-off-by: Pete Skeggs <peter.skeggs@nordicsemi.no>
Added comments to explain the re-use of allocated same
connection context to both 1M and coded PHY scanning context
when both PHY is enabled for initiating connection.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Initial work in progress implementation of Create Connection
Cancel for Extended connection initiation.
Adds implementation to teardown connection initiated at ULL
layer and gracefully release allocated resources.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Added low power configuration to testcase.yaml. In this mode
UARTE is disabled when RX and TX is not used.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Lowest power consumption can be achieved when uarte peripheral
is disabled when not used. In low power mode, need for both
directions is tracked and if both are no in use peripheral is
disabled. TX disabling is instant but RX requires flushing RX
fifo because data in hardware fifo is lost when peripheral is
re-enabled.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Refactored driver to prepare for low power extension. Functional
change is limited to handling of RX_DISABLED event which is now
generated from RXTO interrupt context after RX is stopped. Previously,
RX was not stopped after the transfer.
Rx flushing function contains hardware limitation workaround.
Workaround is applied only if flushed data is not discarded.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
