Commit graph

1222 commits

Author SHA1 Message Date
Krzysztof Chruscinski
fb8be00e05 dts: arm: nordic: Add swo-ref-frequency property
Added swo-req-frequency property to nordic SoC's

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2021-03-15 10:23:10 +01:00
Wojciech Tatarski
bd6617ddf8 dts: add EOS S3 GPIO definitions
Add GPIO definitions to QuickLogic EOS S3 devicetree.

Co-authored-by: Jan Kowalewski <jkowalewski@antmicro.com>

Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com>
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-03-11 08:58:20 -05:00
Erwan Gouriou
29f4574052 dts/arm: stm32: Don't disable systick
In some stm32 series systick was disabled in order to
allow alternate use of lptim timer as kernel low power ticker.
Doing this, dts based definition of CORTEX_M_SYSTICK Kconfig symbol
is disabled and CORTEX_M_SYSTICK was redefined with 'default y'
in stm32 soc files which makes things more complex to handle to
alternate with LPTIM activation.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-03-11 07:10:10 -06:00
MORGER Patrick
986bb53135 dts: arm: stm32g4: Add i2c4
Add DTS configuration for i2c4.

Signed-off-by: MORGER Patrick <patrick.morger@leica-geosystems.com>
2021-03-10 14:57:22 -05:00
Raveendra Padasalagi
772c3620a0 dts: arm: broadcom: viper-a72: paxdma: Add interrupt property
Add interrupt parent and number property specific to a72
viper platform.

Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
2021-03-08 20:24:04 -06:00
Raveendra Padasalagi
b1687ce9da dts: arm: broadcom: viper: rename paxdma label
To keep the generic DMA device name as defined
in the dma framework config, renamed paxdma device
label to "DMA_1".

Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
2021-03-08 20:24:04 -06:00
Mikkel Jakobsen
fbfd75e19a soc: nxp: kl2x: move clk divider options to device tree
Use kinetis SIM clock divider options set in device tree
instead of hardcoded values.

The kl25z device tree did not previously define a MCG node.
This has now been added with the general "nxp,kinetis-mcg"
binding.

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-08 12:18:33 -06:00
Mikkel Jakobsen
2e9500359f soc: nxp: k2x: move clk divider options to device tree
Use kinetis SIM clock divider options set in device tree
instead of kconfig

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-08 12:18:33 -06:00
Mikkel Jakobsen
f0c01561fe soc: nxp: k8x: move clk divider options to device tree
Use kinetis SIM clock divider options set in device tree
instead of kconfig

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-08 12:18:33 -06:00
Mikkel Jakobsen
f218bec877 soc: nxp: kv5x: move clk divider options to device tree
Use kinetis SIM clock divider options set in device tree
instead of kconfig.

The kv5x device tree originally used the undefined
"nxp,kv58-mcg" binding for the MCG node. This has been
replaced by the general "nxp,kinetis-mcg" binding.

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-08 12:18:33 -06:00
Mikkel Jakobsen
68e8a4870d soc: nxp: kwx: move clk divider options to device tree
Use kinetis SIM clock divider options set in device tree
instead of kconfig.

Both the kw40z and kw41z device tree originally used an
undefined "nxp,kw41z-mcg" binding for the MCG node.
This has been replaced with the general "nxp,kinetis-mcg"
binding instead.

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-08 12:18:33 -06:00
Mikkel Jakobsen
f674e82ac4 soc: nxp: k6x: move clk divider options to device tree
Use kinetis SIM clock divider options set in device tree
instead of kconfig

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-08 12:18:33 -06:00
Peng Fan
cefba05a71 dts: qemu: a53: add cpu1 node
Add cpu1 node

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-03-06 07:36:37 -05:00
Alexander Kozhinov
a991ee3be2 dts: arm: st: f4: stm32f446.dtsi
add CAN_1 and CAN_2 hw modules support

Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>

Co-authored-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-03-05 08:30:43 -06:00
Raveendra Padasalagi
8c704ea3a8 soc: viper: update registers and interrupt numbers
Update register addresses and NVIC/GIC interrupt numbers
according to the latest viper RTL version.

Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
2021-03-05 07:21:54 -06:00
Raveendra Padasalagi
30110cd047 dts: arm: rename pl330 dma device label
Rename pl300 device label from "pl330" to "DMA_0"

Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
2021-03-04 12:59:46 +01:00
Mikkel Jakobsen
2d9770d66f dts: nxp: k2x: add device tree node for DAC0 and DAC1
Add device tree nodes for the Digital-to-Analog (DAC) modules present
in the NXP Kinetis K2x series.

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
2021-03-02 16:27:47 -06:00
Alexander Kozhinov
22cb54174a dts: arm: st: f4: stm32f446re
add uart5 to SoC

Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
2021-03-02 16:24:26 -06:00
Kumar Gala
686968b16a dts: arm: nxp: lpc: Add dts nodes for IOCON
Add binding and dts nodes for the IOCON and IOCON ports on the LPC
family of SoCs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-03-01 12:04:53 -06:00
Kumar Gala
1da16553fb dts: stm32: Add exti nodes to stm32 wl series
The STM32 WL dts is missing the exti node.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-28 17:12:04 -05:00
Kumar Gala
ac9d71d689 dts: stm: f1: Fix duplicate label
The dma1 & dma2 controllers had the same label value.  The dma2
controller should really be "DMA_2".

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-25 13:39:32 -06:00
Piotr Pryga
8dcf8c111f dts: bindings: net: wireless: Change dfe-ant-num property name
Change dfe-ant-num propert name to dfe-antenna-num.
The change is conde to keep the same naming style
for all properies, like dfe-pdu-antenna property.

Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
2021-02-25 14:53:27 +01:00
Piotr Pryga
64cb4bbc37 Bluetooth: controller: LLL: DF add initialization of ant switching GPIOs
Add initialization of GPIOs that are used for antenna switching.
GPIOs provided to DFE extension in Radio peripheral, to drive
antenna switching, should be initialized in GPIO peripheral beforehand.
The initialization is optional and may be disabled by Kconfig.

Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
2021-02-25 14:53:27 +01:00
Helge Juul
30dbc40909 drivers/flash: stm32: Extend qspi-nor support to F7 series
Add quadspi node in stm32f7.dtsi and quadspi support to boards
stm32f746g_disco and stm32f769i_disco.
Note! Does not support DMA.

Signed-off-by: Helge Juul <helge@fastmail.com>
2021-02-24 18:12:40 -06:00
Shlomi Vaknin
3b5906ce03 dts: stm32l4: Support sdmmc on stm32l4+
Add device tree bindings for sdmmc controller
on stm32l4+ devices.

Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
2021-02-24 18:10:09 -06:00
Pavlo Hamov
5ae781d7d0 drivers: watchdog: cc32xx: Add support
Impelement watchdog for ti_cc32xx family

Signed-off-by: Pavlo Hamov <pasha.gamov@gmail.com>
2021-02-24 08:35:27 -06:00
Jun Lin
445ecaf8a4 dts/arm: npcx: fix the invert field of JTAG0/1 selection
NPCX chip allows firmware to select the JTAG0/1 via bit 2/1 in the
DEVALT5 register. However, the selection logic is reverse
(i.e. 0:select; 1:not select.)
This change fixes the wrong setting of the invert field.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I2c080feaa7647e940463d9491b61a342c84a6141
2021-02-22 17:57:11 -05:00
Jun Lin
818ef576a2 dts/arm: npcx: fix the size of scfg register
The size of System Configuration register cannot exceed 0x70. Otherwise,
it will overlap the Debug Interface register which starts from
0x400c3074.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2021-02-22 17:57:11 -05:00
Mulin Chao
7c9d3f44f0 driver: sensor: npcx: add tachometer sensor support.
In NPCX7 series, it contains two tachometer (TACH) modules that contains
two Independent timers (counter 1 and 2). They are used to capture a
counter value when an event is detected via the external pads (TA or
TB).

The CL also includes:
— Add npcx tachometer device tree declarations.
— Zephyr sensor api implementation for tachometer.
— Enable "tach1" device in npcx7m6fb.dts for testing.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-02-22 17:56:19 -05:00
Mulin Chao
1f731c6c02 driver: soc: power: npcx: Add power managerment support.
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.

The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.

Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
  power rails.

And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
              time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
              time is greater or equal to 201 ms

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-02-19 22:39:53 -05:00
Mulin Chao
e5caae8e0a driver: timer: npcx: add system kernel timer support.
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.

It includes:
 - A system timer based on an ITIM64 (Internal 64-bit timer) instance,
   clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
 - Its prescaler is set to 1 and provide the kernel cycles reading
   without handling overflow mechanism.
 - A event timer based on an ITIM32 (Internal 32-bit timer) instance,
   clocked by LCLK which frequency is 32KHz and still activated when ec
   entered "idle/deep idle" power state for better power consumption.
 - Its prescaler is set to 1 and provide timeout event mechansim.
 - Compensate system timer which clock is gating for better power
   consumption after ec left"idle/deep idle" power state.

This CL passed starve, timer_api, and timer_monotonic test suites.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-02-19 22:39:53 -05:00
Alexandre Bourdiol
68f5626b64 boards/dts: add SPI support to nucleo_wl55jc board
Add SPI support to nucleo_wl55jc board

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-02-19 22:39:24 -05:00
Alexandre Bourdiol
d98ce0b9d4 boards/dts: add i2c support to nucleo_wl55jc
Add I2C support to nucleo_wl55jc

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-02-19 22:39:24 -05:00
Alexandre Bourdiol
7d11f300b7 dts: arm: st: add STM32WL support
Add STM32WL55Xc device tree

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2021-02-19 22:39:24 -05:00
Pavlo Hamov
ee6ec8d4f3 drivers: adc: cc32xx: Add support
Support 4 channels in IRQ mode. Sync/Async

Signed-off-by: Pavlo Hamov <pasha.gamov@gmail.com>
2021-02-19 10:43:58 -06:00
Harry Jiang
f8251f3bde dts: arm: st: h7: Add the IWDG1 nodes to STM32H7xx SoC
Add the IWDG1 nodes to STM32H7xx Series Soc

Signed-off-by: Harry Jiang <explora26@gmail.com>
2021-02-17 16:19:21 -06:00
Erwan Gouriou
e987d51815 dts: stm32: Add exti nodes to stm32 series
Add exti node for each stm32 series and matching binding description.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-02-17 14:26:23 -06:00
Ioannis Glaropoulos
007c8539f6 dts: arm: nordic: add QDEC nodes for nrf5340
Add device tree nodes for QDEC peripheral instances
for nRF5340 Application core.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2021-02-17 22:34:20 +03:00
Wealian Liao
24d9e31197 dts: npcx7: add support for npcx7m6fc & npcx7m7fc
Add support for Nuvoton npcx7m6fc & npcx7m7fc.

Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
2021-02-17 14:33:03 +01:00
Kumar Gala
b275fec8c4 soc: stm32: convert to use DEVICE_DT_GET for clocks
Convert from device_get_binding to DEVICE_DT_GET.  In doing this we
no longer need the label in the devicetree node so we remove that.

Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-16 17:01:37 -06:00
Kumar Gala
ca5272f239 pinctrl: cc13x2_cc26x2: drop label property from pinmux node
We've removed the need for label properties from the pinmux devicetree
nodes on all other controllers and its not required for the TI one, so
remove it from the .dts and drop label being required in the binding.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-16 16:46:31 -06:00
Kumar Gala
942916e691 arm: nxp: kinetis: Rework device_get_binding for pinmux
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device.  As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-16 16:45:02 -06:00
Kumar Gala
6e8eb53b51 arm: atmel: sam0: Rework device_get_binding for pinmux
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device.  As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-15 08:31:29 -05:00
Kumar Gala
147bb6b9f3 arm: microchip: mec1501hsz: Rework device_get_binding for pinmux
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device.  As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-15 08:29:34 -05:00
Scott Worley
2b926db4e1 drivers: espi: Microchip eSPI add SAF support
Add ESPI SAF features to the Microchip eSPI driver as
a separate file. ESPI SAF depends upon the core eSPI
driver adding the ability to attach the system SPI
flash to the EC eSPI endpoint instead of the host
eSPI controller.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2021-02-15 08:22:01 -05:00
Alexander Wachter
f725719cf1 dts: stm32g4: Add SPI4 node
This commit adds the SPI4 node on the stm32g4 SoC.

Signed-off-by: Alexander Wachter <alexander.wachter@leica-geosystems.com>
2021-02-15 08:20:30 -05:00
Nicolas VINCENT
233162f113 dts: add lpuart1 node for stm32h7 devices
lpuart controller is available on stm32h7, add it to the corresponding
dts file.

Signed-off-by: Nicolas VINCENT <nicolas.vincent@vossloh.com>
2021-02-15 08:20:06 -05:00
Ryan Holleran
b417bb85d2 dts: nxp_k2x: Correct and enable MCG clock controller binding
nxp_k2x.dtsi: Corrects Multipurpose Clock Generator binding
to utilize nxp,kinetis-mcg. Assign MCG to FlexTimer devices.
Enable FlexTimer clocks via System Integration Module clock
gate control registers.

Kconfig.defconfig.mk22f12: Enable default use of
CLOCK_CONTROL_MCUX_MCG when CLOCK_CONTROL is selected.

Signed-off-by: Ryan Holleran <rhollerar@gmail.com>
2021-02-15 08:14:06 -05:00
Mulin Chao
5e5dc358d9 dts/arm: npcx: move def_lvol_io_list node from board dts to dtsi file.
This CL moves def_lvol_io_list device-tree node from npcx7m6fb_evb.dts
to npcx7m6fb.dtsi. The benefit of it is that we needn't add
def_lvol_io_list node for each board dts file if there are no 1.8V
io-pads on the platform. If so, add them in the specific board dts file
directly.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-02-15 08:10:46 -05:00
Francois Ramu
27a3c953a5 dts: arm: stm32wb55 and stm32l4: Add cpu label
Add label to facilitate add cpu-idle-states later.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2021-02-15 08:07:12 -05:00