Add dts files for the specific chip instances that are used on the
boards in prep of having pin data in devicetree. The pin data will
be specific to the given chip instance so we need to distinguish
unique chips for the same SoC as the pin mux will differ.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fixing issue 219727. Potentially negative return value was passed
to a function that was expecting positive value.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Update collaborators and maintainer of some orphaned areas. Also update
path for some of the areas to include tests and samples.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The low power states 0∕1∕2 are added to the stm32wb55rg
nucleo board, with default min residency values.
The substate-id is mapping the same Zephyr power state.
They correspond to the stm32wb55 low power stop0/1/2 modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power states 0∕1∕2 are added to the stm32wb.
The substate-id is mapping the same Zephyr power state.
They correspond to the stm32wb low power stop0/1/2 modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The debug config will let the clocks active in STOP mode
at init.
The substate-id is mapping the same Zephyr power state.
Plus a minor fix in the Kconfig.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Enable MSI hardware auto calibration for this stm32l562
disco board. It depends on the STM_LSE clock.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power states 0∕1∕2 are added to the stm32l562e_dk board
with default min residency values.
The substate-id is mapping the same Zephyr power state.
They correspond to the stm32l562 low power stop0/1/2 modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patch introduces the support of the LowPower Timer
for the STM32l562ze disco kit (sec. and non-sec. version)
LSE clock is selected as LPTIM clock source on this board.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power modes are available on the stm32l5 soc
with the mcu STOP0/1/2 modes, depending on the CONFIG_PM
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patch introduces the support of the Low Power Timer
for the STM32L5xx from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power states 0∕1∕2 are added to the stm32l4.
The substate-id is mapping the same Zephyr power state.
They correspond to the stm32l4 low power stop0/1/2 modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power states 0∕1∕2 are added to the stm32l476rg
nucleo board, with default min residency values.
The substate-id is mapping the same Zephyr power state.
They correspond to the stm32l476 low power stop0/1/2 modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This new release adds support for diffs as well as being able to list
added and removed projects.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
As of today the build-only testing in upstream is enabled for
nsim_em and nsim_em7d_v22 which are very similar from the
compiler POW. The ARC HS, ARC Secure EM and SMP targets miss
any testing.
So adjust default testing for better coverage by enabling
build-only testing for nsim_hs, nsim_sem and nsim_hs_smp and drop
excessive testing for nsim_em7d_v22.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Enabling I2C support for Nucleo-F207zg in device tree.
This has been tested with mpu6050 sample application on I2C-1.
Documentation has been updated.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
Enabling I2C-1,2,3 support for STM32F2 platforms in dtsi.
This has been tested with mpu6050 sample application on I2C-1.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
In the file gatt.c, GAP service contains the Device Name
characteristic. If writable, authentication and authorization may
be defined by a higher layer specification.It means that GATT
clients can write to device name GAP characteristic without
bonding. So we add a configuration for writable name without
bonding.
Signed-off-by: Jun Huang <huangjun6@xiaomi.com>
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
In the function conn_param_update, it should send the opcode
GAP_CONN_PARAM_UPDATE, instead, it send GAP_PASSKEY_ENTRY.
Signed-off-by: Jun Huang <huangjun6@xiaomi.com>
bt_le_oob_set_legacy_tk is not defined with this
setting and this code is reachable only for legacy pairing
signed-off-by: Krzysztof Kopyściński <krzysztof.kopyscinski@codecoup.pl>
Adds a check for the BT_LE_FEAT_BIT_PER_ADV bit for each
function related to periodic advertising, including sync and
PAST transfer.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
When compiling TF-M with profile_medium, disable the support
for Audit Log due to an upstream bug.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Prevent a thread from being preempted, while executing a Secure
function. This is required to prevent system crashes that could
occur if a thead context switch is triggered in the middle of a
Secure call.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
To allow using TFM NS interface without enabling
CMSIS_RTOS V2 support. And to allow using TFM NS
code that uses logging.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The TF-M NS interface needs to be initialized before
it is used. We add an initialization function that
calls tfm_ns_interface_init(), at boot time, so then
we can use TF-M interface calls (veneers).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In ARM Non-Secure builds with TF-M it is not, generally,
possible to issue system reset requests from Non-Secure
domain. When the Platform SPM Partition is enabled, the
tfm_platform_system_reset(.) API can be used to request
system resets from TF-M. This commit overrides the weak
sys_arch_reboot() implementation in scb.c so Non-Secure
code is able to issue system resets.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Instruct CMake to include interface libraries when
building a Non-Secure ARM target with TF-M. In
particular, include the reboot.c source file, which
overrides the sys_arch_reboot implementation.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Populates the onoff server stubs in the Bluetooth Mesh sample, and
implements generic LED based hardware support to include more boards.
Fixes#31031.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
XCC (which is based on GCC 4.2) needs the initializer of
one of the union elements to be enclosed in brackets.
So add them.
Fixes#33549
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There was a linker script change the broke the sorting such that
priority 2 and 20 would not necessary get sorted correctly. Modify
the test to try and catch any such issues in the future.
We modify the DEVICE_DEFINE of the larger priority first, so if the
linker isn't sorting it would get linked first in theory, and we also
tweak the priority value from 4 to 20 so if we aren't sorting correctly
between 2 and 20 we'll catch that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As per the agreements in the Process Group Meeting, rework the procedure
to include external code so that it reflects the reality of Zehyr today
with the choice between modules and integration into the main tree, and
decouple the non-Apache v2.0 license side of the question from the
process from importing 3rd-party code.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
disk/disk_access.h got moved, but there is no compat warning.
Add that so users know they need to update code.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Before this fix the board init function were called too early, before
the gpio driver was initialized. Because of the the board controller
for the serial port was not enabled properly.
This commit fixes this issue.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Hex firmware file is flashed by default if JLink is used. Since all
of the SiLabs dev boards have an on-board JLink, enable generating hex
file.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Add test to check if uart_irq_is_pending() correctly returns 0 (meaning
there are no more RX and TX pending interrupts) when all RX and TX data
is processed.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Currently CMSDK uart_irq_is_pending does not use RX and TX interrupt
bits found in INTSTATUS register to check for pending interrutps but
rather it checks for pending interrupts indirectly by checking if RX and
TX buffers are, respectively, full and empty, i.e. it checks bits 0 and
1 in STATE register instead of bits meant for interrupt status found in
INTSTATUS register.
That is particularly problematic because although a RX interrupt implies
a RX buffer full and a TX interrupt implies a TX buffer empty, the
converse is not true. For instance, a TX buffer might be empty for all
data was processed (sent to serial line) already and no further data was
pushed into TX buffer so it remained empty, without generating any
additional TX interrupt. In that case the current uart_irq_is_pending
implementation reports that there are pending interrupts because of the
following logic:
/* Return true if rx buffer full or tx buffer empty */
return (UART_STRUCT(dev)->state & (UART_RX_BF | UART_TX_BF))
!= UART_TX_BF;
which will return 1 (true) if STATE[0] = 0 (TX buffer is empty), since
UART_TX_BF = 1, so STATE[0] != UART_TX_BF, which is true (assuming here
for the sake of simplicity that UART_RX_BF = 0, i.e. RX buffer is empty
too).
One of the common uses of uart_irq_is_pending is in ISR in contructs
like the following:
while (uart_irq_update(dev) && uart_irq_is_pending(dev)) {
if (uart_irq_rx_ready(dev) == 0) { // RX buffer is empty
continue;
}
// RX buffer is full, process RX data
}
So the ISR can be called due to a RX interrupt. Upon finishing
processing the RX data uart_irq_is_pending is called to check for any
pending IRQs and if it happens that TX buffer is empty (like in the case
that TX interrupt is totally disabled) execution gets stuck in the while
loop because TX buffer will never transition to full again, i.e. it will
never have a chance to have STATE[0] = 1, so STATE[0] != UART_TX_BF is
always true.
This commit fixes that undesirable and problematic behavior by making
uart_irq_is_pending use the proper bits in the interrupt status register
(INTSTATUS) to determine if there is indeed any pending interrupts.
That, on the other hand, requires that the pending interrupt flags are
not clearly automatically when calling the ISR, otherwise
uart_irq_is_pending() will return immediatly false on the first call
without any data being really processed inside the ISR. Thus, because
both RX and TX buffer (FIFO) are only 1 byte long, that commit clears
the proper interrupts flags precisely when data is processed (fifo_read
and fifo_fill) or when the interrupts are disabled (irq_rx_disable and
irq_tx_disable).
Finally, that commits also takes the chance to update some comments,
specially regarding the need to "prime" when enabling the TX interrupts
(in uart_cmsdk_apb_irq_tx_enable()). The need to "prime" can be verified
in the CMSDK UART reference implementation in Verilog mentioned in the
"Arm Cortex-M System Design Kit" [0], on p. 4-8, section 4.3,
in cmsdk_apb_uart.v. In that implementation it's also possible to verify
that the FIFO is only 1 byte long, justifying the semantics that if
buffers are not full (STATE[0] or STATE[1] = 0) they are _completly_
empty, holding no data at all.
[0] https://documentation-service.arm.com/static/5e8f1c777100066a414f770b
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
* Removed leading 0 from slot0_partition starting offset
* Fixed slot1_partition starting offset
This fixes the following warnings:
nucleo_g0b1re.dts.pre.tmp:1749.36-1752.5: Warning
(unit_address_format):
/soc/flash-controller@40022000/flash@8000000/partitions/
partition@0C000:unit name should not have leading 0s
warning: unit address and first address in 'reg' (0x3e000) don't match
for /soc/flash-controller@40022000/flash@8000000/partitions/
partition@31000
Signed-off-by: Raúl Sánchez Siles <rsanchezs@k-lagan.com>
The "spi-max-frequency" property already exists, but was unused. This
now sets the SPI clock frequency to this value (limited to 24MHz) once
initialisation is complete.
Due to the nature of the SPI API, it is necessary to have two separate
configuration structures to switch clock speed as some SPI drivers only
compare pointers to detect changes.
Fixes: #32996
Signed-off-by: Rich Barlow <rich@bennellick.com>
