This serves two main purposes:
- change the CPU clock via devicetree nodes
- provide the APB frequency to device drivers via the clock driver
interface
Theoretically this could also support choosing between the available
clock sources, but right now we only support LPOSC0 going into PLL0,
going into AHB.
Turning the PLL back off is also not supported since the only current
use case is to set the PLL frequency, turn it on, and switch the AHB
over to it.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
This is the bare minimum and includes the SoC, pinctrl, flash and
devicetree.
I had to include the flash driver that early because I couldn't make
Zephyr compile without flash driver nodes in the device tree.
Signed-off-by: Michael Zimmermann <michael.zimmermann@grandcentrix.net>
Introduce riscv_clic_irq_vector_set() to implement z_riscv_irq_vector_set()
for CLIC. This commit also introduces CONFIG_CLIC_SMCLICSHV_EXT to indicate
support for the smclicshv extenion and riscv_clic_irq_vector_set().
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
FCB was being relocated to the wrong location, and the flexspi clock
setup was not being relocated.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add slot type for debug-stream transport over a debug window slot. For
details see src/debug/debug_stream/debug_stream_slot.h under SOF
sources [1].
[1] https://github.com/thesofproject/sof
Signed-off-by: Jyri Sarha <jyri.sarha@linux.intel.com>
ESP32 SoC has multiple revisions, some of which are not supported
by the current implementation, as such as REV0 and REV1. This PR
adds an option to indicate user that this is not recommended and not
supported.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
IMXRT11XX secondary core should not deinit ENET PLL
as it could be configured by primary core.
Signed-off-by: Anders Bjørn Nedergaard <abn@polytech.com>
The nRF9280 is a SiP (System-in-Package) consisting of the nRF9230 SoC
and additional components such as PMIC and others. Additionally,
the nRF9230 contains several CPUs, similarly to the nRF54h20 SoC.
Update nrfx glue, and add necessary Kconfig and initialization code
to allow building for nRF9280 targets: CPU, Radio and PPR cores.
The nRF9280 is used for all user build targets and Kconfigs,
whereas the nRF9230 is used as the build target for the MDK.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Co-authored-by: Andreas Moltumyr <andreas.moltumyr@nordicsemi.no>
Move mpu_region.c to common folder, to re-use with nRF92.
Rename it to nrf54hx_nrf92x_mpu_regions.c to indicate
which product series it applies to.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Move default of monolithic and fw loader, options, etc to the
common kconfig files rather than defaulting in soc file.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Consolidate the ROM RAMLOADER config to be in one place,
add a new Kconfig file to be included by the SOCs with the feature.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The CONFIG_USB_MCUX_CONTROLLER_TYPE choice config
is not necessary, let's just remove it. Theoretically,
if there was an SOC with the EHCI and LPCIP3511, then
it might cause a build error, but there is no SOC
which is supported on this legacy driver that has that.
Remove all settings of it in the SOC files.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Currently this code related to how to configure the
flash size and address when using flexspi to XIP is copy
pasted in all sort of places and ways all over the tree,
let's clean this up and have single point of control over
this configuration.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Move all dependencies of the family config to series level,
and put a disclaimer saying not to use the family config.
Change all occurrences of the family config in code to the
MCXNX4X series config.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
NXP is not supporting these derivative parts in the zephyr upstream,
these references to them should therefore be removed in order to avoid
confusion.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The Kconfig defaults should be in Kconfig.defconfig.
MFD should not be made dependent on the LP flexcomm being
enabled, since MFD can be for other things than just flexcomm.
Change from depends on to an if.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Doesn't seem like there is any reason to be changing the
serial and ADC driver init priorities in the SOC defconfigs.
By default, clock control has priority 30, dma has priority 40,
and serial/adc have priority 50. This seems already to be the order
that is needed, and the original goal of these overrides, which
don't seem necessary anymore.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There are some SOCs which use the same pinctrl
device, but are not really overall that similar to the kinetis
family of SOCs, so prepare to reuse this code by other SOC families.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Moving RT118x kconfigs to series level instead of family level,
and cleaning up redundant declarations, and adding missing
HAS_MCUX_FLEXSPI selection.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
/zephyr/soc/intel/intel_adsp/ace/power.c:46:9: warning: implicit
declaration of function 'cache_data_flush_range'; did you mean
'sys_cache_data_flush_range'? [-Wimplicit-function-declaration]
46 | cache_data_flush_range((__sparse_force void *)
| ^~~~~~~~~~~~~~~~~~~~~~
| sys_cache_data_flush_range
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The symbol DCACHE_LINE_SIZE was not being defined in Intel ADSP
targets.
It fixes the following problem:
/zephyr/soc/intel/intel_adsp/ace/power.c:30:29: error:
'CONFIG_DCACHE_LINE_SIZE' undeclared here (not in a function); did you
mean 'XCHAL_DCACHE_LINESIZE'? 30 | uint8_t
adsp_pending_buffer[CONFIG_DCACHE_LINE_SIZE]
__aligned(CONFIG_DCACHE_LINE_SIZE);
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The Audio integration PLL is faster on PTL compared to earlier ACE
platforms: 442.368 MHz instead 393.216 MHz, however the default
divider remained 16, which will result incorrect cardinal clock speed.
Change the divider to 18 in order to get correct 24.576 MHz cardinal
clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Add initial support for nuvoton npcm400, which is a chip
family of Satellite Management Controller(SMC).
Add ecst python scripts to append the header used by ROM Code
Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: James Chiang <cpchiang1@nuvoton.com>
Signed-off-by: Joseph Liu <kwliu@nuvoton.com>
Enable the NXP Kinetis Low Power Timer (LPTMR) timer driver when
power management is enabled.
When the NXP KE1xZ SoC series is using the Arm SysTick as hardware
timer, the cycles/second will always be equal to the CPU core clock
frequency.
Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
Add support for the stm32h755 which is a close relative of
the stm32h745 with additional cryptography and hashing
peripherals.
Signed-off-by: Mike Banducci <michael.banducci@sandc.com>
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
- Initial support for RA6M2 SoC
Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Danh Doan <danh.doan.ue@bp.renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
