What is changed?
Secondary cores can now boot successfully on cache and non-cache
coherent systems if the Zephyr image/vector table is loaded at an
address other than the default address 0x0.
How is it changed?
1. By calling the relocate_vector() from reset.S as part of EL1 reset
initialization instead of prep_c to have VBAR set for all cores and
not just for the primary core.
2. Remove dead code under CONFIG_SW_VECTOR_RELAY and
CONFIG_SW_VECTOR_RELAY_CLIENT.
Why do we need this change?
1. As reported in issue #76182, on Cortex_ar, VBAR is set only for
the primary cores while VBAR for the secondary cores are left with
default value 0.
This results in Zephyr not booting on secondary cores if the vector
table for secondary cores is loaded at an address other than 0x0.
VBAR is set in relocate_vector() so we move it to reboot.c which is
better suited to have configs related to system control block.
2. The two SW_VECTOR_RELAY configs have a direct dependency on
CONFIG_CPU_CORTEX_M, which is disabled while compiling for
Cortex-A and Cortex-R hence leading to a dead code.
How is the change verified?
Verified with fvp_baser_aemv8r/fvp_aemv8r_aarch32/smp.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
This reverts commit ec7943bb18.
This commit introduced a regression.
Let's revert it so we do not block development in main.
For more information see:
https://github.com/zephyrproject-rtos/zephyr/issues/79594
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Gdb is typically able to reconstruct the first two frames of the
failing stack using the "pc" and "lr" registers. After that, (if
the frame pointer is omitted) it appears to need the stack pointer
(sp register) to point to the top of the stack before a fatal
error occurred.
The ARM Cortex-M processors push registers r0-r3, r12, LR,
{possibly FPU registers}, PC, SPSR onto the stack before entering the
exception handler. We adjust the stack pointer back to the point
before these registers were pushed for preservation in the dump.
During k_oops/k_panic, the sp wasn't stored in the core dump at all.
Apply similar logic to store it when failures occur in that path.
Signed-off-by: Mark Holden <mholden@meta.com>
This reverts commit 88f6851a3d.
This is being reverted because it is redundant with the capabilities of
zephyr,memory-region and zephyr,memory-attr properties.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The `CONFIG_PLIC_IRQ_AFFINITY` depends on `CONFIG_SMP` in the
Kconfig layer, nested #ifdef can be avoided for readability.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This commit introduces architecture-specific ELF relocations for RISC-V,
in accordance with the RISC-V PSABI specification:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
Also, the necessary compiler configurations for compiling LLEXT
extensions on RISC-V are added, and the llext tests are executed on
RISC-V targets.
Calling llext extensions from user threads in RISC-V is still
unsupported as of this commit.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
"in behave of" -> "on behalf of", which is more accurate of
what is actually happening in the code.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
- Implement irq-set-affinity in RISCV PLIC.
- Added new affinity shell command to get/set the irq(s)
affinity in runtime, when `0` is sent as the `local_irq`, it
means set/get all IRQs affinity.
- Some minor optimizations
Updated the build_all test to build this new configuration.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Restore the s0 we saved early in ISR entry so it shows up
properly in the CSF.
Signed-off-by: David Reiss <dreiss@meta.com>
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Enable Cortex R8 support, similar to Cortex-R5.
Signed-off-by: Krzysztof Sychla <ksychla@antmicro.com>
Signed-off-by: Marek Slowinski <mslowinski@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
When building LLEXT for Xtensa with custom sections the compiler
can leave unresolved references in them. Then this has to be done by
the LLEXT core during linking. This commit adds linking support for
the L32R Xtensa instruction.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Red zone was causing issues in places where inline assembly was pushing
data to stack, like arch_irq_lock, and possibly in other places.
Initially -mno-red-zone was enabled on x86_64, but was later, maybe
accidentially, disabled in https://github.com/zephyrproject-rtos/zephyr/
commit/b7eb04b3007767be9febe677924918d2422a4406
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Up until now, the `__thread` keyword has been used for declaring
variables as Thread local storage. However, `__thread` is a GNU
specific keyword which thus limits compatibility with other
toolchains (for instance IAR).
This PR intoduces a new macro `Z_THREAD_LOCAL` which expands to the
corresponding C11, C23 or C++11 standard keyword based on the standard
that is specified during compilation, else it uses the old `__thread`
keyword.
Signed-off-by: Daniel Flodin <daniel.flodin@iar.com>
This adds the bits to call into architecture code to dump
the privileged stack for user threads.
The weak implementation is simply there as a stub until
all architectures have implemented the associated function.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For code clarity, remove unnecessary `return` statements
in functions with a void return type they don't affect control flow.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
`CONFIG_MP_NUM_CPUS` has been deprecated for more than 2
releases, it's time to remove it.
Updated all usage of `CONFIG_MP_NUM_CPUS` to
`CONFIG_MP_MAX_NUM_CPUS`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Do not use SYS_INIT for initializing irq_offload when enabled, instead
using a new interface that is called during the boot process for all
architectures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a new call for initializing cache on architectures that need that.
Avoid using SYS_INIT for this and instead call the hook in a fixed place
and run if implemented.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This adds a kconfig to enable making the interrupts
non-preemptible by other interrupts. Enabling this will set
the INTLEVEL to the max non-debug level before clearing
the EXCM bit.
Signed-off-by: Christopher J. Champagne <christopher.j.champagne@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
nocache ram is usually used by DMA to transfer data between
peripherals and ram. Some chips use isolated nocache ram,
which does not necessarily have to be in RAMABLE-REGION.
By specifying the zephyr,nocache-ram options, users can specify
the region where nocache-ram is located. If the user does not
specify it, it defaults to RAMABLE-REGION.
Signed-off-by: Weiwei Guo <guoweiwei@syriusrobotics.com>
Otherwise we can't escape from DEPRECATED being selected, and so getting
build warnings. It doesn't make sense that the option replacing the
deprecated one is used to automatically enable it.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
If adding/removing to the domain of the current running
thread, we need to update the hardware MPU regions or else
the addition or removal would not be reflected to current
running thread.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a spinlock to make sure writing to hardware MPU
regions is atomic, and cannot be interrupted until all
regions are written to hardware.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Fill the memory of all CPU's IRQ stack with 0xAA on init, so
that `z_stack_space_get` can calculate the remaining space
correctly.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Adds support for all relocation type produced by GCC
on AARCH64 platform using partial linking (-r flag) or
shared link (-fpic and -shared flag).
Signed-off-by: Adam Wojasinski <awojasinski@baylibre.com>
If PSCI is enabled, it will leverage psci reset API to achieve system
reboot, otherwise a weak dump reboot API is provided, and platform
can override these APIs if platform specified implementation provided.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Convention is to call k_mem_page_fault() with IRQs enabled if they were
enabled when the fault occurred.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This has two purposes: maintain the accessed and dirty page states, or
call the generic demand paging fault handler otherwise.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
A page table entry used for demand paging is always from the last level
page table and never completely zeroed. Anything else is considered
ARCH_DATA_PAGE_NOT_MAPPED.
Loaded pages use a PTE_PAGE_DESC table entry type. Paged-out pages use a
PTE_INVALID_DESC table entry type and the physical address field is
reused to hold the backing store location token value.
ARCH_DATA_PAGE_ACCESSED corresponds to the AF flag. It is initially
unset and manually set to catch when pages are being accessed and
eventually do something about it.
ARCH_DATA_PAGE_DIRTY corresponds to the lack of the AP_RO flag.
Similarly to the AF flag, pages are initially made read-only to catch
writes.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Let's consider free entries as being completely zeroed. Future patches
for demand paging support will populate entries and still mark them as
"invalid" which should not be considered free. Current code always clear
entries to be freed so no issues there.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
With this commit, it is now allowed to register any ISR and arg
combination for the same IRQ, except the case when the exact same
ISR-arg combination is already registered.
The previous assert logic had a restriction where the same ISR could not
be registered multiple times with different arguments.
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The callee-saved-registers can be helpful to debug the state of
a core upon an exception, however, currently there's no way to
access that information in user-implemented
`k_sys_fatal_error_handler()`, even though the csf is already stored
in the stack.
This patch conditionally add a `csf` member in the `arch_esf` when
`CONFIG_EXTRA_EXCEPTION_INFO=y`*, which the `_isr_wrapper` would update
when a fatal error occurs before invoking `z_riscv_fatal_error_csf()`.
Functions such as `k_sys_fatal_error_handler()` would then be able
to access the callee-saved-registers at the time of exception via
`esf->csf`.
* For SoCs that select `RISCV_SOC_HAS_ISR_STACKING`, the
`SOC_ISR_STACKING_ESF_DECLARE` has to include the `csf` member,
otherwise the build would fail.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
On 32-bit x86, it was supposed to print the first argument to
the function during stack trace. However, it only works when
code optimizations are totally disabled (i.e. -O0). As such,
printing the args is not meaningful to aid with debugging.
So change it to simply print the function address, the same
as x86 64-bit.
Also, since unwind_stack() has exactly one caller, make it
ALWAYS_INLINE to skip a function call.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
