Commit graph

22 commits

Author SHA1 Message Date
Lucas Tamborrino
11fc182315 soc: esp32: refactor esp32_net
SOC_ESP32_NET is now SOC_ESP32_APPCPU, following espressif's
naming convention in the same manner as ESP32S3 app cpu.

SOC_ESP32_APPCU is now a subset of SOC_SERIES_ESP32.

This commit also changes the necessary files, samples and tests
for bisect purposes.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2024-01-13 00:22:24 +00:00
Sylvio Alves
b19c164e7b soc: espressif: add common linker tls entry
Adds common thread-local-storage.ld provided
by Zephyr. This also fixes a wrong xtensa_core entry
that should be riscv_core.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-01-08 15:09:48 +01:00
Lucas Tamborrino
ff62faac07 soc: xtensa: esp32s2/s3: remove HEAP_MEM_POOL_ADD_SIZE_SOC
There is no need for this config here and it is messing
with total sys heap calculation.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-12-27 10:08:47 +02:00
Johan Hedberg
ec23622b07 soc: xtensa: Use HEAP_MEM_POOL_ADD_SIZE KConfig options
Kconfig options with a HEAP_MEM_POOL_ADD_SIZE_ prefix should be used to
set the minimum required system heap size. This helps prevent
applications from creating a non-working image by trying to set a too
small value.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2023-12-20 11:01:42 +01:00
Daniel Leung
106061b307 xtensa: rename files with hyphens to underscores
Simply to provide some consistencies on file naming under
arch/xtensa.

These are all internally used files and are not public.
So there is no need to provide a deprecation path for
them.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Sylvio Alves
ca346ba216 soc: esp32: call reset cause reason init
Reset cause reason was not initalized properly, making
hwinfo feature not to work as expected.

Fixes #65634

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-11-27 19:59:45 +01:00
Marek Matej
d34f725df8 soc: xtensa: esp32s3: Update SOC variant list
Add missing combinations of the ESP32-S3 Wroom module.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-11-22 21:56:39 +01:00
Torsten Rasmussen
4b02bbc329 cmake: xtensa: update xtensa SoC to use SOC_LINKER_SCRIPT variable
This commit updates all xtensa SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2023-11-03 11:01:23 +01:00
Sylvio Alves
3f5ea785f2 linker: esp32: fix linker to enable proper MMU usage
ESP32 flash_mmap() function requires `_rodata_reserved_start` address
to be at the beginning of RODATA. This allows adding memory-mapped flash
areas.

Fixes #52764

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-10-25 09:57:48 +02:00
Sylvio Alves
4b5331ba45 linker: esp32: move snippets-section within rom boundary
This will guarantee that application snippets will be placed
into ROM section properly.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-10-13 13:10:22 +03:00
Sylvio Alves
bdda8ac48e soc: esp32s3: add esp32s3_appcpu for AMP support
Adds esp32s3_appcpu SoC and update default esp32s3 SoC
to support AMP feature.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-09-27 12:07:21 +02:00
Sylvio Alves
f5fa4b3bcd soc: espressif: provide VMA to rodata and text by default
Flash segments require VMA to proper work. Executing from LMA
is not possible. Current implementation did not take into account
runtime iterable rom sections that any application could implement.
In the above cenario and as reported in the issue below, ESP32 won't run
when those ROM sections are created in application level.

This change make sure all flash segments are properly mapped
accordingly.

Fixes #61834

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-09-18 10:38:03 +01:00
Gerard Marull-Paretas
aaeb0a672e toolchain: only include <zephyr/toolchain.h>
It is wrong to use toolchain-specific header files.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-15 09:27:30 +02:00
Almir Okato
af3b04238e soc: espressif: adjust memory organization on linker
Adjust the memory organization to avoid overlapping
critical regions from bootloaders (MCUboot and IDF)

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2023-08-31 14:08:41 +02:00
Almir Okato
e946a13fe1 soc: espressif: fix SOC series name macro on loader.c
Update macro CONFIG_SOC to CONFIG_SOC_SERIES.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2023-08-31 14:08:41 +02:00
Eric Holmberg
526ff047cc soc: xtensa: espressif_esp32: add SPIRAM heap offset and size
The existing heap starts at the beginning of SPIRAM which is also occupied
by the WiFi stack if CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM is enabled.  This
results in memory corruption.

Update the linker description to add a _spiram_heap_start symbol and add a
KConfig size option to allow the SPIRAM stack to be correctly located and
sized.  Requires matching commit in hal_espressif.

Fixes: 61359

Signed-off-by: Eric Holmberg <eric.holmberg@northriversystems.co.nz>
2023-08-22 14:44:16 +02:00
Daniel Leung
3c3f480be8 esp32: rename shadow variables
Rename shadow variables found by -Wshadow.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-08-22 11:39:58 +02:00
Sylvio Alves
bcb59b8f46 soc: esp32s3: fix heap_sentry reference
Fix heap_sentry value to point final useful stack area.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-08-16 15:03:57 +02:00
Gerard Marull-Paretas
3118a8c05c soc: riscv|xtensa: esp32: add support for sys_poweroff
Implement the sys_poweroff hook for all ESP32 SoCs based on the previous
SOFT_OFF implementation.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-15 10:15:38 -07:00
Lucas Tamborrino
47515f4d7b soc: xtensa: esp32s3: Add external ram noinit section
Add section to allocate memory of WiFi and NET stack in SPIRAM

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-07-26 14:42:20 +02:00
Lucas Tamborrino
c435dea191 soc: xtensa: esp32s3: add support for SPIRAM
Add support for external PSRAM for esp32s3.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-07-26 14:42:20 +02:00
Marek Matej
6b57b3b786 soc: xtensa,riscv: esp32xx: refactor folder structure
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:

- changing the CONFIG_SOC_ESP32* to refer to
  the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
  the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
  provide a SOC model config
- introducing the 'common' folder to hide all
  commonly used configs and files.
- updating west.yml to reflect previous changes in hal

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-25 18:12:33 +02:00