Commit graph

43960 commits

Author SHA1 Message Date
Anas Nashif
a180b33c55 timing: add support for nordic SoCs with RTC timer
Add abstraction for nordic SoCs using Nordic RTC as the source for
timestamps and cycles.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-09-05 13:28:38 -05:00
Anas Nashif
d896decb79 timing: add support for x86
Add initial support for X86 and get timestamps from tsc.

Authored-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-09-05 13:28:38 -05:00
Anas Nashif
5dec235196 arch: default timings for all architectures
Use default if architecture does not have a custom timing
implementation.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-09-05 13:28:38 -05:00
Daniel Leung
0ffcfa9633 timing: introduce timing functions as a generic feature
Add timing functions and APIs.  This is now used with some of the tests
we have for performance and metrics and will be used whereever timing
informations are needed, for example for tracing, profiling and other
operations where timing info is critical.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-09-05 13:28:38 -05:00
Daniel Leung
80fb6538b3 x86: use =A as output for RDTSC on x86-32
The timing_info benchmark on qemu_x86 shows this is a bit faster.

Before:
  START - Time Measurement
  Timing results: Clock frequency: 1000 MHz
  Context switch                               : 896 cycles ,   895 ns
  Interrupt latency                            : 768 cycles ,   767 ns
  Tick overhead                                :14912 cycles , 14911 ns
  Thread creation                              :18688 cycles , 18687 ns
  Thread abort (non-running)                   :49216 cycles , 49215 ns
  Thread abort (_current)                      :55616 cycles , 55615 ns
  Thread suspend                               :11072 cycles , 11071 ns
  Thread resume                                :10272 cycles , 10271 ns
  Thread yield                                 :12213 cycles , 12212 ns
  Thread sleep                                 :17984 cycles , 17983 ns
  Heap malloc                                  :21702 cycles , 21701 ns
  Heap free                                    :15176 cycles , 15175 ns
  Semaphore take with context switch           :19168 cycles , 19167 ns
  Semaphore give with context switch           :18400 cycles , 18399 ns
  Semaphore take without context switch        :2208 cycles ,  2207 ns
  Semaphore give without context switch        :4704 cycles ,  4703 ns
  Mutex lock                                   :1952 cycles ,  1951 ns
  Mutex unlock                                 :7936 cycles ,  7935 ns
  Message queue put with context switch        :20320 cycles , 20319 ns
  Message queue put without context switch     :5792 cycles ,  5791 ns
  Message queue get with context switch        :22112 cycles , 22111 ns
  Message queue get without context switch     :5312 cycles ,  5311 ns
  Mailbox synchronous put                      :27936 cycles , 27935 ns
  Mailbox synchronous get                      :23392 cycles , 23391 ns
  Mailbox asynchronous put                     :11808 cycles , 11807 ns
  Mailbox get without context switch           :20416 cycles , 20415 ns
  Drop to user mode                            :643712 cycles , 643711 ns
  User thread creation                         :652096 cycles , 652095 ns
  Syscall overhead                             :2720 cycles ,  2719 ns
  Validation overhead k_object init            :4256 cycles ,  4255 ns
  Validation overhead k_object permission      :4224 cycles ,  4223 ns
  Time Measurement finished

After:
  START - Time Measurement
  Timing results: Clock frequency: 1000 MHz
  Context switch                               : 896 cycles ,   895 ns
  Interrupt latency                            : 768 cycles ,   767 ns
  Tick overhead                                :14752 cycles , 14751 ns
  Thread creation                              :18464 cycles , 18463 ns
  Thread abort (non-running)                   :48992 cycles , 48991 ns
  Thread abort (_current)                      :55552 cycles , 55551 ns
  Thread suspend                               :10848 cycles , 10847 ns
  Thread resume                                :10048 cycles , 10047 ns
  Thread yield                                 :12213 cycles , 12212 ns
  Thread sleep                                 :17984 cycles , 17983 ns
  Heap malloc                                  :21702 cycles , 21701 ns
  Heap free                                    :15176 cycles , 15175 ns
  Semaphore take with context switch           :19104 cycles , 19103 ns
  Semaphore give with context switch           :18368 cycles , 18367 ns
  Semaphore take without context switch        :1984 cycles ,  1983 ns
  Semaphore give without context switch        :4480 cycles ,  4479 ns
  Mutex lock                                   :1728 cycles ,  1727 ns
  Mutex unlock                                 :7712 cycles ,  7711 ns
  Message queue put with context switch        :20224 cycles , 20223 ns
  Message queue put without context switch     :5568 cycles ,  5567 ns
  Message queue get with context switch        :22016 cycles , 22015 ns
  Message queue get without context switch     :5088 cycles ,  5087 ns
  Mailbox synchronous put                      :27840 cycles , 27839 ns
  Mailbox synchronous get                      :23296 cycles , 23295 ns
  Mailbox asynchronous put                     :11584 cycles , 11583 ns
  Mailbox get without context switch           :20192 cycles , 20191 ns
  Drop to user mode                            :643616 cycles , 643615 ns
  User thread creation                         :651872 cycles , 651871 ns
  Syscall overhead                             :2464 cycles ,  2463 ns
  Validation overhead k_object init            :4032 cycles ,  4031 ns
  Validation overhead k_object permission      :4000 cycles ,  3999 ns
  Time Measurement finished

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-09-05 13:28:38 -05:00
Daniel Leung
c234821861 x86: use LFENCE instead of CPUID before reading TSC for x86_64
According to Intel 64 and IA-32 Architectures Software
Developer’s Manual, volume 3, chapter 8.2.5, LFENCE provides
a more efficient method of controlling memory ordering than
the CPUID instruction. So use LFENCE here, as all 64-bit
CPUs have LFENCE.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-09-05 13:28:38 -05:00
Daniel Leung
8197bdea2b tests: timing_info: remove timing info
Remove this benchmark which was relying on custom tracing points in the
code and was not scalable. Use latency_measure benchmark instead which
is more realistic and measures similar metrics in a fully reproducible
manner and on all supported architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-09-05 13:28:38 -05:00
Johann Fischer
362d8b27a7 drivers: usb_dc_mcux_ehci: fix endpoints index assignment
MCUX EHCI USB device controller supports a specific
number of bidirectional endpoints. Bidirectional means
that an endpoint object is represented to the outside
as an OUT and an IN Eindpoint with its own buffers
and control structures.

ep_abs_idx index refers to the corresponding control
structure, for example:

 EP addr | ep_idx | ep_abs_idx
-------------------------------
 0x00    | 0x00   | 0x00
 0x80    | 0x00   | 0x01
 0x01    | 0x01   | 0x02
 0x81    | 0x01   | 0x03
 ....    | ....   | ....

The NUM_OF_EP_MAX (and number of s_ep_ctrl) should be double
of num_bidir_endpoints. There is also no need to reserve
endpoint addresses for this controller type.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
2020-09-05 10:49:37 -05:00
Henrik Brix Andersen
2f95794b29 doc: releases: 2.4: add EEPROM release notes for v2.4
Add EEPROM release notes for v2.4.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2020-09-05 10:26:58 -05:00
Torsten Rasmussen
9aa4039d41 cmake: MWDT linker command list fix.
This commit fixes an issue where the list returned by
zephyr_get_include_directories_for_lang() would be a space separated
list, cause the arguments to be quoted during linking.

This is fixed by requesting `$<SEMICOLON>` to be used as separated which
which again ensures a correct expansion of the list.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2020-09-05 10:22:56 -05:00
Torsten Rasmussen
571f48fc77 cmake: mwdt bintools adopted to new toolchain abstraction
This commit converts the MWDT bintools implementation from the old
macro based approach and into the new toolchain property scheme.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2020-09-05 10:22:56 -05:00
Torsten Rasmussen
93e063ffc8 cmake: mwdt compiler adopted to new toolchain abstraction
This commit converts the MWDT compiler implementation from the old
macro based approach and into the new toolchain property scheme.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2020-09-05 10:22:56 -05:00
Eugeniy Paltsev
05b6468a73 ARC: linker: add more place for optimization
Do not force linker to place text sections after each other
to have more freedom to optimize.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Eugeniy Paltsev
3a9bc23ad9 ARC: SOC: NSIM: fix CMakeLists indentation
No functional changes intended

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Eugeniy Paltsev
6dfaac0c95 cmake: allow to specify compliler for DTS preprocessing
MWDT CCAC compiler can't handle the dts file as gcc does, so
allow to specify compliler for DTS preprocessing which is differ
from ${CMAKE_C_COMPILER}.

Use ARC GNU compiler for DTS preprocessing in case of MWDT
toolchain.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Eugeniy Paltsev
a28ec6201f isr_tables: don't whole-archive library
As of today we have a bit weird situation with generated
sw_isr_table / irq_vector_table tables.

On the final linkage stage we pass two files which content
section with sw_isr_table / irq_vector_table. They are
 * libarch__common.a (with an outdated tables from the first
   linkage stage)
 * isr_tables.c.obj (with an actual tables)

The sections where tables are located are marked with
".gnu.linkonce" prefix. That means:
<<<As a GNU extension, if the name begins with .gnu.linkonce,
we only link a single copy of the section.>>>

However the "libarch__common.a" is passed to linker with
"--whole-archive" option which means <<<include every object
file in the archive in the link, rather than searching the archive
for the required object files>>>

That combination confuses MWDT linker and breaks linkage with
MWDT toolchain.

As a simple fix we can move the sw_isr_table / irq_vector_table
sections to their own library and link this library with
"--no-whole-archive" option.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Wayne Ren
53e1d9866f ARC: board: nsim: enable metaware toolchain in sanitycheck
Enable MWDT toolchain in sanitycheck for all ARC nSIM boards

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Eugeniy Paltsev
f609a9acd8 ARC: soc: add MWDT compiler options for nsim targets
Add metaware compiler options for nsim targets

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Wayne Ren
b868018b51 cmake: add metaware toolchain support in build system
* add metaware toolchain support in build system:
   * compiler
   * linker
   * binutils
     * gcc objcopy is used because it can't be replaced
       with mwdt's binutils currently
* To use ARC metaware toolchain, you'd better:
   * in Linux/Unix environment
   * install arc gcc/zephyr toolchain to use gnu's objcopy
     tool
   * set ZEPHYR_TOOLCHAIN_VARIANT=arcmwdt

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Eugeniy Paltsev
2167ffbe45 ARC: toolchain: handle difference in macros for MWDT and ARC GNU
Create include/toolchain/mwdt.h to handle difference in
several macros for MWDT and ARC GNU toolchains.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Eugeniy Paltsev
c2bb7db3fd ARC: linker: implement linker related definition for MWDT
Implement linker related definitions and macros for MWDT
toolchain.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Eugeniy Paltsev
0a7b65ef5e linker: tweak section naming to feet all linkers
MWDT toolchain adds additional suffix to sections name in case of
ffunction-sections / fdata-sections are enabled.

As proposed by Andy Ross let's pick a single set of rules
and syntax that work.

Suggested-by: Andy Ross <andy@plausible.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Eugeniy Paltsev
6b8f92be08 app_memdomain: ARC: adjust asembler directives for MWDT toolchain
ARC MWDT assembler has slightly different directives names:
.pushsect instead of .pushsection
.popsect instead of .popsection

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Wayne Ren
cc897a5198 ARC: add linker script template for metware toolchain
Add linker script template for MWDT toolchain (linker-mwdt.ld)
Move linker.ld to linker-gnu.ld (without changes)

The "linker.ld" is wraper now.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2020-09-05 10:22:56 -05:00
Eugeniy Paltsev
0227056066 ARC: change direct IRQ declaration for metaware toolchain
* change direct IRQ declaration for metaware toolchain
* drop unused irq-related definitions

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Eugeniy Paltsev
932e178007 ARC: use MWDT intrinsics to access aux regs in case of MWDT toolchain
Metaware doesn't support gcc's builtins so use corresponding intrinsics
instead.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Wayne Ren
fb05bfce05 ARC: rename arch_switch implementation to z_arc_switch
"arch_switch" is declared as an inline function in kswap.h,
it should be a wrapper of arch level switch. The difference
of declaration and implementation of "arch_swich" causes
warning from MWDT compiler.

Use "arch_switch" with proper declararion (which is just
wraper for "z_arc_switch") to do conext switch for ARC.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Wayne Ren
ef224ce1cd ARC: make the assembly codes compatible
Make the assembly codes compatible with both GNU
and Metaware toolchain.

* replace ".balign" with ".align"
  ".align" assembler directive is supposed by all
  ARC toolchains and it is implemented in a same
  way across ARC toolchains.
* replace "mov_s __certain_reg" with "mov __certain_reg"
  Even though GCC encodes those mnemonics and even real
  HW executes them according to PRM these are restricted
  ones for mov_s and CCAC rightfully refuses to accept
  such mnemonics. So for compatibility and clarity sake
  we switch to 32-bit mov instruction which allows use
  of all those instructions.
* Add "%%" prefix while accessing registers from inline
  ASM as it is required by MWDT.
* Drop "@" prefix while accessing symbols (defined in C
  code) from ASM code as it is required by MWDT.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>

/#
2020-09-05 10:22:56 -05:00
Eugeniy Paltsev
596cd869c3 ARC: sys_io: rewrite to C code
Replace ASM sys_io implementation with identical C code for ARC.
This significantly improves portability, i.e. compiler decides
which instructions to use for a particular CPU and / or
configuration.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Wayne Ren
d67475ab6e ARC: handle the difference of assembly macro definition
GNU toolchain and MWDT (Metware) toolchain have different style
for accessing arguments in assembly macro. Implement the
preprocessor macro to handle the difference.

Make all ASM macros in swap_macros.h compatible for both ARC
toolchains.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-09-05 10:22:56 -05:00
Carlo Caione
df4aa230c8 arch: arm64: Use _arch_switch() API
Switch to the _arch_switch() API that is required for an SMP-aware
scheduler instead of using the old arch_swap mechanism.

SMP is not supported yet but this is a necessary step in that direction.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2020-09-05 12:06:38 +02:00
Maksim Masalski
fd15524912 tests: arch: arm mem protection check CPU scrubs regs after syscall
To improve Zephyr security, I decided to create a test
test_after_syscall_cpu_scrubs_regs
I think necessary to check upon exit of a system call back
to the calling thread, the kernel scrubs CPU registers for sensitive
data.

Signed-off-by: Maksim Masalski <maksim.masalski@intel.com>
2020-09-05 11:53:39 +02:00
Francois Ramu
9a94168e78 disk: sdhc: use the multiple block transfer for writing
The sdhc_spi_write_multi function is sending the CMD25
for multiple block write operation on the SD card
instead of looping the CMD24. This is improving
the transfer speed compared to the sdhc_spi_write function
when the nb of blocks to write is significant (more than 2).

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-09-05 11:07:04 +02:00
Martí Bolívar
c505ca38cf scripts: west build: default build.pristine to auto
I've repeatedly seen that people are not aware of the existence of
this configuration option.

I've been using build.pristine=auto daily for years and never had any
problems. I've also asked around on Slack a couple of times over
various points to see if anybody objects to making this change. Nobody
has, so let's just turn it on by default.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-09-05 11:06:39 +02:00
Luiz Augusto von Dentz
95cec8354c Bluetooth: GATT: Introduce bt_gatt_attr_get_handle
This introduces bt_gatt_attr_get_handle which can be used to resolve
handles of static attributes.

Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
2020-09-05 11:06:21 +02:00
Luiz Augusto von Dentz
5c4bde55d0 Bluetooth: GATT: Rework bt_gatt_attr_func_t
Make it actually give the original pointer to the attribute and its
resolved handle so static attributes don't need an extra lookup.

Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
2020-09-05 11:06:21 +02:00
Luiz Augusto von Dentz
dde25a3d44 Bluetooth: GATT: Optimize static service handle resolution
This optimizes the lookups to skip ahead when attribute pointer is not
located within service array.

Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
2020-09-05 11:06:21 +02:00
Flavio Ceolin
b62f2df5d4 toolchain: gcc: Fix fallthrough attribute for old versions
fallthrough attribute was introduced in gcc 7. For older versions the
macro is empty to avoid the follow warnning:

~/zephyrproject/zephyr/lib/os/printk.c:268:5: warning: empty declaration
     __fallthrough;

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2020-09-04 22:25:17 -04:00
Andrew Boie
47b4a5c47b test: thread_stack: relax ram requirement
Possibly copypasta, or improvements to the test, either way
this test doesn't use that much RAM especially if memory
protection isn't active.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-09-04 22:24:48 -04:00
Gerson Fernando Budke
0656fd3833 west.yml: update hal_atmel for SAM4L
Update hal_atmel to include vendor files for SAM4L SoC series.

see zephyrproject-rtos/hal_atmel/pull/13.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-09-04 16:29:19 -05:00
Gerson Fernando Budke
7ce1bf7928 boards: arm: atmel: Introduce sam4l_ek board
Add initial version.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-09-04 16:29:19 -05:00
Gerson Fernando Budke
bca8e83cab drivers: hwinfo: sam: Add sam4l hwinfo support
Add initial version.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-09-04 16:29:19 -05:00
Gerson Fernando Budke
4e1d6af8f8 dts: hwinfo: Add atmel sam4l unique serial number
Add ATMEL SAM4L hwinfo bindings to get unique 120 bits serial number.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-09-04 16:29:19 -05:00
Gerson Fernando Budke
ab31a2e543 soc: arm: atmel: Introduce sam4l SoC
Introduce SAM4L SoC initial files.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-09-04 16:29:19 -05:00
Gerson Fernando Budke
18e608ee55 dts: arm: atmel: Introduce sam4l SoC
Introduce SAM4L SoC device tree definitions.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2020-09-04 16:29:19 -05:00
David Leach
7b0d7906ab boards: arm: Fix conditionalized pinmuxes for shared pin
A change was put in to conditionalize pinmuxes based on
Ethernet configuration but for the IMXRT1050/60/64-EVK
boards the USER_LED and ENET_RST share the same GPIO.
Samples like blinky would not work on these boards.

The change is to not conditionalize the shared pin.

fixes: #27473

Signed-off-by: David Leach <david.leach@nxp.com>
2020-09-04 14:07:50 -05:00
Luiz Augusto von Dentz
67041a85d2 Bluetooth: shell: Add CONFIG_BT_AUDIO
This enables use of iso module with shell application.

Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
2020-09-04 21:03:13 +02:00
Luiz Augusto von Dentz
b8e9b6f88a Bluetooth: shell: Add iso module
This adds iso shell module which we can be used to exercise ISO related
APIs:

iso - Bluetooth ISO shell commands
Subcommands:
  bind        :[dir] [interval] [packing] [framing] [latency] [sdu]
  [phy] [rtn]
  connect     :Connect ISO Channel
  listen      :[security level]
  send        :Send to ISO Channel
  disconnect  :Disconnect ISO Channel

Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
2020-09-04 21:03:13 +02:00
Luiz Augusto von Dentz
d85d40c58e Bluetooth: hci_raw: Add support for ISO packets
This adds supports for ISO packets so then can be transmitted and
received with hci_raw driver.

Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
2020-09-04 21:03:13 +02:00
Luiz Augusto von Dentz
f93c4dece0 Bluetooth: userchan: Add support for ISO packets
This adds supports for ISO packets so then can be transmitted and
received with userchan driver.

Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
2020-09-04 21:03:13 +02:00