This commit defines the bt-hci subnode under the bleif node on
Ambiq Apollo3 Blue and Apollo3 Blue Plus SOC.
Also add the default configurations for Bluetooth feature on Ambiq
apollo3_evb and apollo3p_evb.
Signed-off-by: Aaron Ye <aye@ambiq.com>
This commits add the BLEIF instance which is compatible with
"ambiq,spi-bleif" on Ambiq apollo3p_evb and apollo3_evb.
Also creates the default pinctrl for the defined instance.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Some Ambiq Apollox Blue SOC (e.g. Apollo3 Blue) uses internal designed
BLEIF module which is different from the general IOM module for SPI
transceiver. The called HAL API will also be independent. This driver is
implemented for the BLEIF module usage scenarios.
Signed-off-by: Aaron Ye <aye@ambiq.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.
This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.
It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
- Add initial version of CYW920829M2EVK-02 board
- [drivers: clock_control] Make it possible to set up both iho and imo
clocks instead of just one or the other
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Secondary cores are not allowed to be power gated on
runtime-idle. They have to explicitely set off by host command.
Remove this state from secondary CPUs so power management logic
does not need workarounds to enforce this behavior.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The MBOX driver interface expects a device tree property '#mbox-cells'
which is not known by the IPM driver. This causes build problems when
both drivers are given for a single shared DT node.
To fix this problem for this driver specifically, add a dummy
'#mbox-cells' property to the bindings of the STM32 HSEM IPM driver.
This does not affect any other IPM driver, and the STM32 HSEM IPM driver
is still functioning with this dummy property.
Signed-off-by: Celina Sophie Kalus <hello@celinakalus.de>
Add a device tree binding for the new driver. Since there already
exists an IPM driver using the unsharable hardware semaphore interrupt,
the new driver is not added to any boards or SOCs per default to avoid
compatibility problems. See #37300 for the IPM driver.
Signed-off-by: Celina Sophie Kalus <hello@celinakalus.de>
Add a definition of SUIT storage, so there will be a common source of
the SUIT storage location for both SDFW and scripts generating SUIT
storage areas, assigned to local domains.
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
Add support for the memory controller by utilizing QSPIC2. The latter is
capable to drive both NOR and PSRAM memory devices. For this to work,
the RAM driving mode is enabled.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
This commit adds support for the I2C which
can be found in Apollo3 SoCs, it can work in
both DMA and non-DMA modes
Signed-off-by: Hao Luo <hluo@ambiq.com>
Add bindings for NXP MIPI CSI-2 Rx which is a MIPI CSI-2 receiver
connecting a camera sensor to the NXP CSI.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
TLC59731 is a 3-Channel, 8-Bit, PWM LED Driver with
TI Single-Wire interface (EasySet) protocol.
Signed-off-by: Javad Rahimipetroudi <javad.rahimipetroudi@mind.be>
Convert the ST7735R display to use the MIPI DBI API. Boards and overlays
using this display are also updated.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The RTXXX and RW61X DT are using syscon compatible
depsite not having a syscon. This is a technical debt
to remain aware of. The reason they use these compatibles
is to use the syscon driver which is a shim to an SDK API
that is somewhat similar to syscon.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Include reset device binding in some of the NXP LPC
IP bindings to be able to add the resets property.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add binding representing the peripheral reset controller
of the NXP LPC SYSCON heritage hardware including SYSCON
itself and the newer RSTCTL.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Clarify that there needs to be a cell named "id" in order
to be usable by the reset controller macros.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- Fix mcxn94x flash write-block-size from 16 to 128.
- Fix flash_program() return error 0x65,
that means "Address or length does not meet the required alignment."
- The mcxn94x Flash ROM API flash_program() start address and
the length must be 128 bytes-aligned.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
port infineon CAT1A (psoc6) to HWMv2:
1. move dts\arm\cypress\** to dts\arm\infineon\cat1a\legacy
2. remove dts\arm\cypress\**
3. rename dts\arm\infineon\psoc6 to dts\arm\infineon\cat1a
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Previous value just activated the ability to trigger for both edges,
without (de)-activating the gpio. This caused an assrtion error in GPIO.h.
Fixes#71227
Signed-off-by: Juliane Schulze <juliane.schulze@deveritec.com>
Remove the "snps,designware-spi" compatible from the EXMIF node in
nRF54H20i, as the spi_dw driver cannot be used for this peripheral
without Nordic-specific modifications that are not present upstream.
An attempt to do so (just setting CONFIG_SPI=y will cause that,
as the driver initialization function will be executed then) results
in a bus fault.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Although we can get the number of configured OUT and IN endpoints and
endpoint capabilities from the DWC GHWCFGn registers, we need to
configure the number of endpoint configuration structs at build time. On
some platforms, we cannot access the hardware register at pre-init, so
we use the GHWCFGn values from the devicetree to provide endpoint
capabilities. This can be considered a workaround, and we may change the
upper layer internals to avoid it in the future.
Also, add a new vendor quirk to fill in platform-specific controller
capabilities.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
