This include seems redundant as the driver builds fine without
it being included. When including soc.h it also causes issues
if one utilises the xenvm board when compiling. I suggest this
is removed completely as it seems unnecessary to create this
tight coupling to a specific SoC as the driver implementation
is describing itself perfectly well, and works well without
this soc.h-file.
Signed-off-by: Kent Stark Olsen <kent.stark.olsen@gmail.com>
The Xilinx xuartps driver fails to find the correct pre-scaler
parameters for the BAUDDIV and BAUDGEN registers. This fix
corrects that behaviour. The reason why it fails is due to
the stop condition for the search being ill-conditioned.
The stop condition is based on a baudrate error, and this
was chosen to be 3 percent. This would cause the parameter
search to stop too early returning ill-condotioned pre-scaler
parameters. This has been corrected by setting the stop condition
to be 3 permille instead of 3 percent. This change was tested
with an AMD Zynq Ultrascale+ MPSoC ZU3EG.
Signed-off-by: Kent Stark Olsen <kent.stark.olsen@gmail.com>
hw_wdt_dev may not be NULL and the device not be ready to be used.
If that is the case we explicitely initialize task_wdt_init with
NULL and do not use hw watchdog.
Signed-off-by: Flavio Ceolin <flavio@hubblenetwork.com>
This was inspired by the detection of 2 instances of the warning:
warning: 'strncpy' specified bound 16 equals destination size
[-Wstringop-truncation]
The current code is already safe with regards to overflows, because
fixed-length string functions are used in the call tree. However, when
given a name 16 chars or larger, the current compare in llext_by_name()
will not work as expected because the stored extension name is truncated
to a max of 15.
Define a global LLEXT_MAX_NAME_LEN constant to simplify all this logic
and also implement name checks in the shell before calling llext_load().
Finally, using strlen() instead of strnlen() gets the real length of the
hex string passed as a parameter, which is important for the next safety
check.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Makes the sample build only in automatic test CI
Running on the nucleo_f411re board requires hsi enable
Running on the nucleo_wba55cg can still output the console
on the usart1 Tx even if the usart1Rx is used by the MCO output
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Clarify the documentation in the README.rst file. Also remove the
obsolete comment from main.c as it is no longer correct.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
Replace manually authored hardware features table with the new Zephyr
board supported hardware directive which automatically generates an
up-to-date table based on the boards' Devicetree.
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
Instead of hardcoding a set of paths and trying to find the JLink
executable in them, use the corresponding Windows registry to locate it:
`HKEY_CURRENT_USER\\Software\\SEGGER\\J-Link`
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The logic to detect the default JLink location was placed at the top of
the script, executing whenever the script was imported. The west
extension command framework loads all runners when initializing, and so
this logic was being executed even when using another runner.
Move the logic to a function that is only executed when the JLink runner
is selected, to avoid executing it at all times.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The first two partitions in padconfig mmr regions need to be unlocked for
the pinctrl driver to be able to write. However, the base addresses for the
the registers can be different across SoCs and domains. Besides, currently
this is only done for M4 and that too not in the local (M4's) view.
This patch introduces a file specifying all ctrl partition base addresses
using ifdef directives for different SoCs and variants, and unlocking them
before the kernel and drivers initialize.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
-Update the ETH_STM32_HAL menu configuration to conditionally
select USE_STM32_HAL_RIF if SOC_SERIES_STM32N6X is enabled.
-Align Ethernet descriptors to 32 bytes for STM32N6 to ensure
efficient DMA operations and improve cache line efficiency
and overall performance
-Add RISAF configuration in eth_initialize function for STM32N6
series to set up master and slave security attributes
for the Ethernet peripheral.
-Ensure RISAF configuration is done before enabling
the Ethernet clock to maintain proper security attributes.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Update STM32N6 pinctrl dtsi files with the ETH pins
Add STM32N6 Ethernet pinctrl config to stm32-pinctrl-config.yaml
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
When converting raw values to integer and fractional (micro) parts, the
fractional part must be a signed integer.
- Fix prototypes where the fractional part was declared as unsigned.
- Fix comments which did not match the declared type.
Signed-off-by: Christophe Tournery <christophe.tournery@freshape.com>
Currently, the L2 PPP won't work with AF_PACKET socket family as it only
supports packets from AF_INET/AF_INET6 families. Because of this, it's
not possible to use AF_PACKET RAW or DGRAm sockets with PPP interfaces,
as the packets they generate have family field set to AF_PACKET.
Fix this, by verifying the LL protocol field in the PPP L2 before
passing the packet the respective PPP driver. If the AF_PACKET packet is
received, and the protocol field is set to IP/IPv6, update the packet
family to AF_INET/AF_INET6 accordingly.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Use %zu for size_t and %zd for ssize_t, and don't use those specifiers for
any other type. Also make sure that field width specifiers get typecast to
the expected int type.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
There is a configuration of the DCDC in the clock_init for the RT10xx.
The RT11xx has a kconfig flag ADJUST_DCDC to enable or disable DCDC
adjust code. This flag is now also used for the RT10xx to be able to
enable or disable the DCDC adjust code.
Signed-off-by: Adrian Bieri <adrian.bieri@loepfe.com>
Currently, siwx917 have three instances of uart: ulpuart, uart1 and
uart2. However:
- The other drivers on siwx91x (i2c, dma, i2s, etc...) rather use
'ulp', '0' and '1'.
- The reference manual also uses 'ulp', '0' and '1'.
The source of the confusion probably come from the clock driver in
WiseConnect which use clocks USART1 and USART2. However, this probably
not expected.
So, this patch renames uart1 and uart2 in uart0 and uart1. This change
also impacts the names of pins and the names of the clocks.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
WiseConnect documentation says:
Default value of 100 millisecs is used when
SL_WIFI_DEFAULT_ACTIVE_CHANNEL_SCAN_TIME is passed".
However, this is not true. Currently, DEFAULT_ACTIVE_CHANNEL_SCAN_TIME
is 0xFFFF and the scan time is set to 65 seconds.
To have the default scan time, the value '0' must be used.
Fortunately, '0' is also the value we get when the user does not specify
any default scan time. So the code can be simplified.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Allow to configure the preemtiveness of the ethernet rx-thread independent
of the traffic-class queue.
Signed-off-by: Cla Mattia Galliard <cla-mattia.galliard@zuehlke.com>
Replaced the `-r nrfjprog` option with `-r nrfutil` in the flashing
instructions for the nRF5340 Audio DK board.
NCSDK-30139.
Signed-off-by: Grzegorz Ferenc <Grzegorz.Ferenc@nordicsemi.no>
Several devices have hardware-specific additional limits for
how short a sleep cycle can be. Add an entry for devices based
on Silabs sleeptimer when the OS tick rate is equal to the timer
frequency.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
In the case where more than a full tick was unannounced when
sys_clock_set_timeout() was called, the timer driver would
subtract it from the next timeout. However, this is already
done by the caller through the elapsed() function in timeout.c,
leading to the timer interrupt firing too early.
With this fix, SYS_CLOCK_TICKS_PER_SEC can be increased to the
full speed of the low frequency timer. The underlying sleeptimer
API must be called with a timeout of at least 1, and will if needed
increase the value to the minimum value required by the hardware.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add device tree support for ST Morpho connector pins on the
nucleo-g474RE board, enabling access to GPIO pins available
on both left and right morpho headers.
Signed-off-by: Thomas Günther <thomas.guenther@limatica.com>
Replaced the read-modify-write sequence with a single read and write
operation, preventing the intermediate value is wrongly used to filter
out logs of another thread with higher priority that preempts the current
thread.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
This commit moves the assignment of backend IDs from the 'z_log_init'
function to the earlier 'log_core_init' function. This ensures that
backend IDs are assigned before they are used in the 'log_backend_enable'
function, preventing incorrect settings of log dynamic filters.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Added Kconfig options to allow use of TWIM frequency
workaround in NRFX for nRF52 and nRF53.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
The adsp_mm_save_context function was previously mapping memory without
explicitly setting write permissions, which could lead to a "store
prohibited" exception when attempting to write to the memory. This patch
adds the K_MEM_PERM_RW flag to the arch_mem_map call to ensure that the
memory is mapped with write permissions.
This change resolves the issue of accessing memory without the necessary
permissions, preventing potential exceptions and ensuring correct memory
operations. The issue was found when running the firmware on a
simulation with the MMU enabled.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
