- Allow more statical allocations by reordering the sections
in the mcuboot.ld and in default.ld.
- Reorder the ROM sections to cover the cases described in
the `common-rom-common-kernel-devices.ld`.
Changing the order of .rodata and .text we prevents to create an
overlapped segments issue.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This driver could end up doing a great deal of work inside the ISR when
large SPI transfers were in use, which could cause significant IRQ
latency. For the normal, non-async SPI transfer case, use events to
signal the calling thread to complete the work rather than performing
FIFO transfers inside the ISR.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add an optional DT property to specify the size of the RX/TX FIFO
implemented within the SPI core. The property name used is the same one
used by Xilinx's device tree generator.
When the FIFO is known to exist, we can use the RX FIFO occupancy register
to determine how many words can be read from the RX FIFO without checking
the RX FIFO empty flag after every read. Likewise with the TX FIFO, we can
use the FIFO size to avoid checking the FIFO full flag after every write.
This can increase overall throughput.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add support for a workaround required when using the Xilinx Quad SPI core
with the USE_STARTUP option, which routes the core's SPI clock to the
FPGA's dedicated CCLK pin rather than a normal I/O pin. This is typically
used when interfacing with the same SPI flash device used for FPGA
configuration. In this mode, the SPI core cannot actually take control
of the CCLK pin until a few clock cycles are issued, which would break
the first transfer issued by the core. This workaround applies a dummy
command to the connected device to ensure that the clock signal is in the
correct state for subsequent commands.
See Xilinx answer record at:
https://support.xilinx.com/s/article/52626?language=en_US
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Normally the return code of `CodeChecker analyze` and `CodeChecker parse`
is suppressed, so all the enabled commands can execute instead of
crashing the build.
Add a new option, `CODECHECKER_PARSE_EXIT_STATUS`, to permit failing the
build if `CodeChecker parse` returns non-zero.
Signed-off-by: Noah Pendleton <noah.pendleton@gmail.com>
The deadline of deadline scheduler should lager than zero
because if deadline is negative, it menas the task should
be finished in past.
Signed-off-by: TaiJu Wu <tjwu1217@gmail.com>
intel_adsp_hda_set_buffer() asserts when the HDA buffer is
outside of RAM space. However, it uses CONFIG_SRAM_SIZE as
if it is bytes. In reality, CONFIG_SRAM_SIZE is in KB so
we need to multiply it by 1024, or simply use marco KB().
Fixes#74250
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There actually is no triple faults on Xtensa. Once PS.EXCM is
set, it keeps going through double exception vector for any
new exceptions. However, our exception code needs to unmask
PS.EXCM to enable register window operations. So after that,
any new exceptions will go through the kernel or user vectors
depending on PS.UM. If there is continuous faults, it may
keep ping-ponging between double and kernel/user exception
vectors that may never get resolved. Since we stash DEPC
during double exception, and the stashed one is only cleared
once the double exception has been processed, we can use
the stashed DEPC value to detect if the next exception could
be considered a triple fault. If such a case exists, simply
jump to an infinite loop, or quit the simulator, or invoke
debugger.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
arch_user_string_nlen() did not exactly work correctly as any
invalid pointers being passed are de-referenced naively, which
results in DTLB misses (MMU) or access errors (MPU). However,
arch_user_string_nlen() should always return to the caller
with appropriate error code set, and should never result in
thread termination. Since we are usually going through syscalls
when arch_user_string_nlen() is called, for MMU, the DTLB miss
goes through double exception. Since the pointer is invalid,
there is a high chance there is not even a L2 page table
associated with that bad address. So the DTLB miss cannot be
handled and it just keeps looping in double exception until
there is another exception type where we get to the C handler.
However, the stack frame is no longer the frame associated
with the call to arch_user_string_nlen(), and the call return
address would be incorrect. Forcing this incorrect address as
the next PC would result in some other exceptions, e.g.
illegal instruction, which would go to the C handler again.
This time it will go to the end of handler and would result
in thread termination. For MPU systems, access errors would
simply result in thread terminal in the C handler. Because of
these reasons, change the arch_user_string_nlen() to check if
the memory region can be accessed under kernel mode first
before feeding it to strnlen().
Also remove the exception fixup arrays as there is nothing
there anymore.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a new function xtensa_mem_kernel_has_access() to
determine if a memory region can be accessed by kernel threads.
This allows checking for valid mapped memory before accessing
them to avoid relying on page faults to detect invalid access.
Also fixed an issue with arch_buffer_validate() on MPU where
it may return okay even if the incoming memory region has no
corresponding entry in the MPU table.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
arch_buffer_validate() is only to verify that user threads have
access to the memory region. It should not be used to verify
if kernel thread has access (which they should anyway). So
change the logic.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Introduce CONFIG_XTENSA_BREAK_ON_UNRECOVERABLE_EXCEPTIONS to
use BREAK instruction for unrecoverable exceptions. This
definitely requires debugger to be attached to the hardware
or simulator to catch that.
Also move the infinite loop to NOT result in an infinite
interrupt storm as the debug interrupt will be triggered over
and over again. Same for the simcall exit as it does not
need to be called repetitively.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
If there are any TLB misses during interrupt handling,
the user, kernel and double exception vector will be triggered
for the miss and the DEPC and EXCCAUSE overwritten as the TLB
missse are be handled in the assembly code and execution
returned to the original vector code. Because of this, both
DEPC and EXCCAUSE being read in the C handler are not the ones
that triggered the original exception (for example, level-1
interrupt). So stash both DEPC and EXCCAUSE such that
the original cause of exception is visible in the C handler.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Xtensa MPU code does not handle double exception in C. So there
is no need to clear DEPC on C handler exit.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
We have frame pointer struct and BSA struct to extract
the exception cause (exccause). There is no need to
resort to custom assembly to do that. Besides, given
that the BSA is different between different Xtensa cores,
there is no guarantee it is at the same place as what
the assembly assumes. So just do that without assembly.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simple blinky example, but using STOP3 mode. When in STOP3 mode,
GPIOs are not driven, but only pull-up or pull-down can be enabled
based on value in PWR registers.
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
LPTIM is not available in STOP3 mode, so RTC needs to be used instead.
This code usese similar approach as STM32WBAx for suspend to ram.
The STOP3 is disabled by default in device tree.
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
Fix timing in suspend-to-ram when using STM32WBA.
Switch to use RTC timer should be done only when idle is set
and LPTIM clocks should be switched off
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
Added check if ccc_values[i].attr != NULL,
before accessing to ccc_values[i].attr structure:
(handle == ccc_values[i].attr->handle)
On 20829 platform it's causing hard fault, not sure about
another platforms (in GAP testing).
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
- enable hw-flow-control for uart2
- added p3_0_scb2_uart_cts, p3_1_scb2_uart_rts in **-pinctrl.dtsi
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
This style is used in sensor drivers. It's more complicated than the
other way, which is used in different drivers that are not sensor
drivers.
Signed-off-by: Trent Piepho <tpiepho@gmail.com>
The existing code rounded the result to an integer, then multiplied that
integer by 1000000 to get micro-degrees or micro-percent, and then
divided by 1000000 to get whole degrees/percent and took the modulus to
get fractional degrees/percent.
Obviously, multiplying and then dividing an integer by the same value
has no effect!
The result is the humidity and temperature were always rounded down to
the nearest integer.
Fix this to properly keep the fractional component. This is done in a
way that avoids any integer divisions, which are slow on all CPUs, but
especially most microcontrollers, e.g. Cortex-M, lack any integer
division instruction.
Avoiding the base 10 math does not require more code. One just needs to
think in binary and use binary fractions instead of base 10 fractions.
Signed-off-by: Trent Piepho <tpiepho@gmail.com>
The low two bits are not part of the data, but rather "status" bits that
should be masked off.
This is documented in the HTU21D datasheet Edition 8, date 05/2017, pp.
15, and Sensirion SHT21 datasheet version 6, date 10/2022, §6 (wording
exactly the same):
"The two status bits, the last bits of LSB, must be set to ‘0’ before
calculating physical values."
Also Silicon Labs Si7006 example driver code:
/* Swap the bytes and clear the status bits */
return ((data.byte[0] * 256) + data.byte[1]) & ~3;
Since these are the LSBs, it has only a small effect and might not have
been noticed despite being wrong.
While editing this code, switch to using the Zephyr endian conversion
functions intead of a written out conversion.
Add error code to error log message.
Signed-off-by: Trent Piepho <tpiepho@gmail.com>
These three sensor types are all largely compatible. The SHT21 and
HTU21D can be supported by this driver by sending command 0xE3 instead
of 0xE0 to read the temperature.
Mention the sensor names in bindings and Kconfig to help those looking
for support to find it. There have been at least five PRs attempting to
add SHT21 and/or HTU21D support that did not realize the Si7006 is the
same.
As mentioned in PR #22862, the Sensirion SH21 is the original. The dts
bindings are adjusted (in a backward compatible way!) to make the sht21
the base binding and si7006 is derived from that.
Examples of dts compatibles:
TE Connectivity née Measurement Sepcialties HTU21D:
compatible = "meas,htu21d", "sensirion,sht21";
Sensirion SHT21:
compatible = "sensirion,sht21";
Silicon Labs Si7006
compatible = "silabs,si7006";
Silicon Labs Si7021
compatible = "silabs,si7021", "silabs,si7006";
Signed-off-by: Trent Piepho <tpiepho@gmail.com>
After changing the VEVIF and BELLBOARD names,
the dts for the individual boards must be aligned.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Renaming 'LOCAL' to 'RX' and 'REMOTE' to 'TX'.
This seems more descriptive and intuitive to use.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Add a mailbox driver for VEVIF events (VPR irq).
The driver can be built in either 'rx' or 'tx' configuration.
The VPR sends the event, so it uses the 'tx' configuration,
while the master core uses the 'rx' configuration of the driver
to receive the VPR events.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Extend the coverage tool to handle applications that generate multiple
gcov dumps in a single execution. This can happen when the application
calls `sys_reboot`.
Handling multiple dumps enables coverage testing of exception handlers.
Signed-off-by: Jordan Yates <jordan@embeint.com>
If `sys_reboot` is called during testing, the standard dump when `main`
returns will never be executed. Failing to dump at this point means any
coverage information gathered will be lost upon reboot.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Don't attempt to lock the scheduler is trying to dump coverage
information from an ISR. The scheduler won't run while the ISR is in
progress.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The sample is added to demonstrate mspi_transceive asynchronously.
Apollo3 MSPI controller has hardware command queue and supports
scatter IO and callback management, so no additional software queue
is required.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
The sample code is copied from spi_flash. To flash API, there is no
difference if the bus is spi or mspi.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
The ATXP032 is a NOR flash device that supports up to ~100MHz
octal SDR/DDR with 4MB nonvolatile memory.
The device driver uses MSPI bus API and could be used across different
SoC controllers that implement the MSPI bus API.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
The APS6404L psram is a quad SDR SPI device that runs up to 100MHz.
It can provide 8MB of external RAM for SoCs that supports XIP feature.
The device driver uses MSPI bus API and could be used across
different controllers that implement the MSPI bus API.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
The Ambiq MSPI controller is implemented using the MSPI bus API.
The hardware supports up to 48MHz octal SDR with XIP, scrambling and
hardware command queue features.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
