In the default configuration, cv32a6 does not have an FPU and does not
implement RISC-V's F and D extensions.
Hence, the FPU flags should not be added.
In the future, a second SoC for cv32a6 systems with FPU can be added.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The original commit uses the incorrect value 42 for
CONFIG_MAX_IRQ_PER_AGGREGATOR for the cva6 family of SoCs,
which is the total number of IRQs in the system.
This commit corrects this to 30, the number of IRQs for the PLIC.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
In hardware, cva6 currently only provides global disable/enable
functions for the Dcache and Icache. Disabling and re-enabling them also
has the effect of flushing and invalidating the cache.
Future cva6 SoCs will add support RISC-V's standardized cache management
operations.
This commit provides a default implementation for all methods currently
part of the cache API. These implementations can be overwritten at board
or SoC level, as they use weak linking.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
Adds support for the CVA6 family of RISC-V CPUs.
CVA6 is commonly found as a soft core CPU on FPGA designs.
Different configurations and instruction set extensions can be
configured, and different SoCs targeting various FPGA boards are
available.
This commit adds support for the 32-bit and 64-bit configurations
of CVA6, as well as three slightly different SoCs (a minimal 32-bit
configuration, a 64-bit configuration without FPU, a 64-bit
configuration with FPU).
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
