The interrupt-map property specifies both 32-bits values and a phandle;
update the type accordingly.
Update the definition of pcie-host-ecam-generic on qemu arm64 to match
the new type.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Add board, project, and twister configuration for qemu_kvm_arm64 support
on ivshmem-plain test.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Cited commit requires the limits.h header to fetch the defintion of
INT_MAX, which is missing today. The build process fails without it.
Fixes: cb5c5519e4 ("arch/arm64: Support runtime frequency")
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Add board, project, and twister configurations for QEMU ARM64 support for
ivshmem-plain test.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
The ivshmem-plain test does not use MSI at all; remove the dependency
from the project configuration.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Move the existing ivshmem test to a folder that explicitly identifies
its target: ivshmem-plain. The existing test is not compatible with
ivshmem-doorbell.
ivshmem-doorbell has additional requirements compared to -plain
(ivshmem-server, notification handling), so it is reasonable that
another test is required for it. This commits prepares the way for the new
test.
No funcional change intended.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Add DTS information for qemu-virt-a53 and qemu-kvm-arm64 for PCIe
controller support. Three new bindings are required for the PCIe
controller in ECAM mode.
The DTS information was extracted from QEMU (dumpdtb) with a PCIe device
attached to the virtual machine (ivshmem)
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
For architectures that rely on a PCIe controller (for example, ARM64),
scanning the PCI space will only succeed after the controller has
initialized. Therefore, in the presence of PCIe controller, the PCIe
initialization is bumped to the next system init level.
In the past, drivers like ivshmem would do a late scan of the PCI space
in case the early scan failed; however, the cited commit removed this
feature and ivshmem fails for ARM64. This commit fix this by making the
early scan succeed.
Fixes: a96016d747 ("drivers: ivshmem: Remove unnecessary BDF lookup ...")
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Only include the MSI header when ivshmem-doorbell is employed, as the
ivshmem data structures already use the same protection for msi-related
structures.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
The ivshmem code does not use any platform-specific code; therefore,
remove the dependency to the soc interface.
No functional change intended.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Add a Kconfig option allowing users to configure the transfer timeout
value, as the default 500 ms may not be sufficient in specific cases.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The DFU documentation has been extended with MCUboot API
chapter and API reference, from mcuboot_api Doxygen group.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The Flash img API is used for writting image application image
to flash and is rather part of DFU than storage.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Starting with commit b9b43a0eb772a464bba13833d11e3a31fbf4e09e, printk()
messages are handled by the logging subsystem. This can cause trouble
in watchdog related samples if the deferred logging mode is used (and
currently it is by default), because those samples are ended by a reset
and some messages may not get a chance to be outputted.
Since the same problem concerns also the ordinary logging messages that
may be produced during execution of the samples, this commit fixes it
by switching to the immediate logging mode, not by just disabling the
LOG_PRINTK option.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
In multi-image environment, after jump to the image we can have UART in
unexpected state. Reset UART to default state to make sure that UART is
initialized properly and won't cause system to crash or hang.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
We are about to add UART reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
In multi-image environment, after jump to the image we can have running
timer with interrupts enabled. If interrupt is triggered, the asserts
in the driver can cause a crash.
This patch also adds 'resets' property for all timer nodes.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
We are about to add timer reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
To deassert reset in STM32MP1 RCC the driver needs to set the bit in
reset clear register.
This patch extends existing implementation to support this type of
register.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This driver exposes STM32 RCC reset functionality through reset API.
Information about RCC register offset and bit is encoded just like GD32.
The first 5 least significant bits contains register bit number.
Next 12 bits are used to keep RCC register offset. Remaining bits are
unused.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Setting LOG_LEVEL to 0 was not covered. It resulted in the
logging misbehavior when module logging level was set using
LOG_LEVEL define method and it was set to 0. Instead of
filtering all levels it was applying the default filtering.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The following testcases fail with qemu_cortex_r5 caused by main stack
overflow.
tests/kernel/workq/work_queue/kernel.workqueue
tests/ztest/base/testing.ztest.base.verbose_0_userspace
The main stack size is 512 for qemu_cortex_r5(a Cortex-A/R aarch32
platform) with CONFIG_ZTEST=y. The Cortex-M platforms are already set to
1024. Likely 512 will fail for most aarch32 platforms soon.
Fix the issue by increasing the CONFIG_MAIN_STACK_SIZE to 1024.
Also, remove 'default 1024 if TEST_ARM_CORTEX_M' since Cortex-M is no
longer an exception of default 1024.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Introducing common pdu struct declarations for conn param req/rsp and
data length req/rsp to utilize identicality for optimal pdu handling
Signed-off-by: Erik Brockhoff <erbr@oticon.com>
If a central or peripheral is not configured for ISO connected streams,
reject a remote LL_CIS_TERMINATE_IND procedure, responding with an
unsupported feature error (BT_HCI_ERR_UNSUPP_FEATURE).
This fixes EBQ test /LL/PAC/CEN/BV-01-C.
Signed-off-by: Morten Priess <mtpr@oticon.com>
For making handle available in vendor sink creation, add ISO handle
to function prototype.
Expose datapath allocation via new ull_iso_datapath_alloc function.
Signed-off-by: Morten Priess <mtpr@oticon.com>
Function ll_setup_iso_path has a construction which causes proprietary
compiler to generate incorrect code. As a workaround, local data path
pointer variables are eliminated.
Signed-off-by: Morten Priess <mtpr@oticon.com>
For framed case, the internal RX SDU counter would increment regardless
of whether the first valid SDU was received or not. According to spec,
SDU counter synchronization is done from first valid SDU.
Signed-off-by: Morten Priess <mtpr@oticon.com>
Make sure ll_iso_stream_connected_get returns NULL until CIS is
established. Always return DISALLOWED when trying to disconnect a CIS
which is not connected.
Signed-off-by: Morten Priess <mtpr@oticon.com>
When a CIS is terminated, the associated link pool must be de-
initialized to be ready for next creation of the corresponding
instance in memory.
Signed-off-by: Morten Priess <mtpr@oticon.com>
Specification states that: "Only one Client Characteristic Configuration
declaration shall exist in a characteristic definition." This was
wrongly understood as "Ony one CCC can exist in GATT Server". When we
add next characteristic `ccc_added` flag is cleared so next CC can be
added (for this characteristic).
Added array for CCC values so it's no longer shared between CCCs.
Signed-off-by: Krzysztof Kopyściński <krzysztof.kopyscinski@codecoup.pl>
