Timer STM32 LPTIM currently supports 2 clocks sources: LSE & LSI.
LSE (external) is defined as default but its availability depends
on board support package and then may not be available.
This ends up in situations where users have LSE implicitly selected
while no crystal is available on board, leading to non functional
LPTIM.
To avoid this situation, makes LSI clock, which is always available
(since internal to the SoC), the default LPTIM source clock.
Then, default case will be functional. Users will then be able to
select LSE if needed.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
interrupt controller, also places its relevant
peripheral sources allowing drivers to use the
DT macros instead of espressif headers.
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
When SMP is enabled all the cores are announcing a tick and this is
causing too many ticks to be announced. Announce the tick even if this
is zero.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
If CYC_PER_TICK does not divide the (now - last_count) quantity exactly with integer math, the subsequent multiplication before incrementing last_count causes a drift. This commit eliminates the redundant division-followed-by-multiplication and fixes https://github.com/zephyrproject-rtos/zephyr/issues/37852
Signed-off-by: Berend Ozceri <berend@recogni.com>
This function wasn't being defined when SMP_BOOT_DELAY was set or when
SMP wasn't enabled. There's no reason for either, then function
doesn't depend on any kconfig-dependent build-time state, and (given
that we use -ffunction-sections) it won't appear in output binaries
unless called.
And there are use cases (e.g. z_smp_start_cpu()) where we need that
function even when BOOT_DELAY is enabled.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The free run timer will be used to count before entering hibernate
mode. Move the related registers to the head file for accessing.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
We add disable event timer at the beginning of critical section
for two reason:
1.For K_TICKS_FOREVER case: since no future timer interrupts
are expected or required, so we disable the event timer.
2.Others case: according it81202 spec, when timer enable bit
from 0->1, the timer will reload counts and start countdown.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Instead of putting object files inside libzephyr.a,
simply build a separate static library as most other
driver types are doing this already.
Also sort the entries alphabetically.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add config macro to set interrupt as level triggered for ARM CPUs
Merge all timer configures into one place, then no need to overwrite
hpet_timer_conf_get/set() functions in SoC layer
Make hpet_timer_comparator_set() as the only register access function
to implemented in the SoC layer
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Instead of passing target states, use actions for device PM control.
Actions represent better the meaning of the callback argument.
Furthermore, they are more future proof as they can be suitable for
other PM actions that have no direct mapping to a state. If we compare
with Linux, we could have a multi-stage suspend/resume. Such scenario
would not have a good mapping when using target states.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Since the state is no longer modified by the device PM callback, just
use the state value.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Update Microchip XEC RTOS timer driver adding MEC172x support and
using more device tree properities in the driver. We must also update
the XEC counter driver to use the new GIRQ DT properties.
Add new properties to RTOS timer and RTC timer YAML. These two timers
are linked due to option using a high speed timer for kernel busy wait.
Add Kconfig logic for XEC RTOS timer to MEC172x SoC.
Enable the Microchip XEC RTOS timer in the MEC172x evaluation board.
Add device tree nodes for most peripeherals.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
z_smp_init() is only available if CONFIG_SMP is defined,
smp_timer_init() also depends on two Kconfig parameters. Also make it
conditional in cavs_timer.c. Also clarify some SMP-related comments
there.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This converts register access from macro to functions.
This allows SoCs to override these functions if needed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This allows the HPET timer to use kconfig to specify clock
frequency instead of relying on calculation at runtime.
When the frequency is known at build, this allow the toolchain
to optimize some calculations.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This renames MIN_DELAY to HPET_CMP_MIN_DELAY, and also allows it
to be overridden. The default delay is for HPET with relative
high frequency, and may not suitable for all HPET
implementations.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This extracts the hard-coded value into a macro which can be
overridden. This is in preparation for SoCs where the period
is not in femptoseconds.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
RTC interrupt was reading CC value and passing it to the handler.
However, higher priority interrupt could preempt RTC interrupt
and set new CC value. In that case CC value read in the RTC
interrupt context was not the one that triggered the interrupt.
Added fallback to COUNTER value if that case is detected.
Using COUNTER is not as precise as CC because it returns time
when event was handled and not when event occured but it is the
only option since CC value is overwritten.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Add NXP Kinetis Low Power Timer (LPTMR) OS timer driver shim. Since the
LPTMR does not support asynchronous changes to the timer period, only
non-tickless mode is supported.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The callback is not used anymore, so just delete it from the pm_control
callback signature.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
For esp32c3 related ROM located functions instead
of esp32c3_rom.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
by adding the soc specific files such: soc initialization code,
linker scripts and support for esp32c3 devkitm
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Move all PM_DEVICE_STATE_* definitions to an enum. The
PM_DEVICE_STATE_SET and PM_DEVICE_STATE_GET definitions have been kept
out of the enum since they do not represent any state. However, their
name has not been changed since they will be removed soon.
All drivers and tests have been adjusted accordingly.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Fix for Issue#35658.
Update the custom vector table to add the OS Event timer
interrupt which is used on RT685 as the kernel system timer
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add the lptim1 device node definition and enable the corresponding
exti interrupt in sys_clock_driver_init().
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
Convert the various device_get_binding() calls used to get the device
clock node to use DEVICE_DT_GET. The latter is processed at link time,
so it should be a bit more efficient.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The stm32_lptim driver is hardcoded to use lptim1.
Make the Kconfig option depend on the presence of the node label in the
devicetree, so that there's one less list of supported SoC to keep track
of.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
In npcx series, we use ITIM64 as system kernel timer. Its source clock
frequency must equal to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC. This CL
added check during initialization to prevent ambiguous condition.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Make the APIC_TIMER_IRQ_PRIORITY Kconfig depend on APIC_TIMER ||
APIC_TSC_DEADLINE_TIMER to hide it in menuconfig when not applicable.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
As per description of the sys_clock_elapsed() function, "the kernel
will call this with appropriate locking, the driver needs only provide
an instantaneous answer". Remove then the unnecessary locking from the
function, as it only adds an undesirable delay.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Replace suffix ull to ULL to increase code readability and prevent
unexpected behaviours, because the lowercase character l shall not be
used in a literal suffix
Found as a coding guideline violation (MISRA R7.3) by static
coding scanning tool.
Signed-off-by: Maksim Masalski <maksim.masalski@intel.com>
With this patch the sys_clock_set_timeout function counts the cycles
elapsed while computing the systick timer's new load (tickless mode).
This cycles are then added to the total cycle count instead of being
lost.
This patch mitigates uptime drifting in tickless mode (especially when
high frequency timers are registered).
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
-ENOSYS should be returned if the operation is not implemented. This
issue was causing some PM tests to fail, as -ENOSYS was expected.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The context parameter used across device power management is
actually the power state. Just use it and avoid a lot of
unnecessary casts.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Modern hardware all supports a TSC_DEADLINE mode for the APIC timer,
where the same GHz-scale 64 bit TSC used for performance monitoring
becomes the free-running counter used for cpu-local timer interrupts.
Being a free running counter that does not need to be reset, it will
not lose time in an interrupt. Being 64 bit, it needs no rollover or
clamping logic in the driver when presented with a 32 bit tick count.
Being a proper comparator, it will correctly trigger interrupts for
times set "in the past" and thus needs no minimum/clamping logic. The
counter is synchronized across the system architecturally (modulo one
burp where firmware likes to change the adjustment value) so usage is
SMP-safe by default. Access to the 64 bit counter and comparator
value are single-instruction atomics even on 32 bit systems, so it
beats even the RISC-V machine timer in complexity (which was our
reigning champ for "simplest timer driver").
Really this is just ideal for Zephyr. So rather than try to add
support for it to the existing APIC driver and increase complexity,
make this a new standalone driver instead. All modern hardware has
what it needs. The sole gotcha is that it's not easily emulatable
(qemu supports it only under kvm where they can freeload on the host
TSC) so it can be exercised only on hardware platforms right now.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Remove the config BOOT_TIME_MEASUREMENT and corresponding #ifdef'd code
throughout (kernel/init.c, idle.c, core/common.S , reset.S, ... ) which
hold the extern hooks for z_timestamp_main and z_timestamp_idle in the
removed boot_time test suite.
Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
irq_enable() should be called with the composite IRQ code as its
argument, not just the Xtensa proper part of it.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
During polling ITEN bit to make sure ITIM timer is enabled, we might
have the chance that npcx_itim_evt_enable() return fake error when
timeout expired but ITEN bit is set already if CONFIG_ZERO_LATENCY_IRQS
is enabled. (Since SVCall's interrupt priority is not the highest, the
other interrupts with IRQ_ZERO_LATENCY flag could preempt CPU resource
at this moment.)
In order to prevent return fake error code, this CL adjusts the check
conditions for ITEN bit and timeout.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Compare Match Timer is a 32 bit compare match timer
that can be found on various Renesas R-Car SoC.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
