Commit graph

8 commits

Author SHA1 Message Date
Gerard Marull-Paretas
aaeb0a672e toolchain: only include <zephyr/toolchain.h>
It is wrong to use toolchain-specific header files.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-15 09:27:30 +02:00
Almir Okato
af3b04238e soc: espressif: adjust memory organization on linker
Adjust the memory organization to avoid overlapping
critical regions from bootloaders (MCUboot and IDF)

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2023-08-31 14:08:41 +02:00
Almir Okato
e946a13fe1 soc: espressif: fix SOC series name macro on loader.c
Update macro CONFIG_SOC to CONFIG_SOC_SERIES.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2023-08-31 14:08:41 +02:00
Eric Holmberg
526ff047cc soc: xtensa: espressif_esp32: add SPIRAM heap offset and size
The existing heap starts at the beginning of SPIRAM which is also occupied
by the WiFi stack if CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM is enabled.  This
results in memory corruption.

Update the linker description to add a _spiram_heap_start symbol and add a
KConfig size option to allow the SPIRAM stack to be correctly located and
sized.  Requires matching commit in hal_espressif.

Fixes: 61359

Signed-off-by: Eric Holmberg <eric.holmberg@northriversystems.co.nz>
2023-08-22 14:44:16 +02:00
Sylvio Alves
bcb59b8f46 soc: esp32s3: fix heap_sentry reference
Fix heap_sentry value to point final useful stack area.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-08-16 15:03:57 +02:00
Lucas Tamborrino
47515f4d7b soc: xtensa: esp32s3: Add external ram noinit section
Add section to allocate memory of WiFi and NET stack in SPIRAM

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-07-26 14:42:20 +02:00
Lucas Tamborrino
c435dea191 soc: xtensa: esp32s3: add support for SPIRAM
Add support for external PSRAM for esp32s3.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-07-26 14:42:20 +02:00
Marek Matej
6b57b3b786 soc: xtensa,riscv: esp32xx: refactor folder structure
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:

- changing the CONFIG_SOC_ESP32* to refer to
  the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
  the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
  provide a SOC model config
- introducing the 'common' folder to hide all
  commonly used configs and files.
- updating west.yml to reflect previous changes in hal

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-25 18:12:33 +02:00