Convert from device_get_binding to DEVICE_DT_GET. In doing this we
no longer need the label in the devicetree node so we remove that.
Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove conditionals (PM_DEEP_SLEEP_STATES and PM_SLEEP_STATES) from
power management code. Now these features are always available when
power management is enabled.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Migrate the whole pm subsystem to use new power states information
from power_state.h and get states and residency properties from
device tree.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The cc13xx_cc26xx driver uses "inst" so we need to use
DEVICE_DT_INST_DEFINE instead of DEVICE_DT_DEFINE.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The spi_nrfx_spis driver uses nodelabel so we need to use
DEVICE_DT_DEFINE instead of DEVICE_DT_INST_DEFINE.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
- Remove SYS_ prefix
- shorten POWER_MANAGEMENT to just PM
- DEVICE_POWER_MANAGEMENT -> PM_DEVICE
and use PM_ as the prefix for all PM related Kconfigs
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Use the devicetree node as the source of object name and other
information used when defining the device structure.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Change to spi_context_lock missed one spot in the flexcomm driver and
this causes a build issue. Pass spi_cfg to spi_context_lock to fix
the issue.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
On the STM32MP1 and STM32H7 Series SoC, if slave select pin control by
software on master mode operation, the SS input/output polarity (SSIOP)
should be set to high level avoid the mode fault (MODF) error.
Signed-off-by: Harry Jiang <explora26@gmail.com>
Keep locking for SPI_LOCK_ON from the first call of transceive until
spi_release release the lock. Use owner parameter to in the spi_context
to store the owner of the lock.
The locking is in line with the SPI_HOLD_ON_CS
Signed-off-by: Stefan Bigler <stefan@bigler.io>
For drivers that support CONFIG_DEVICE_POWER_MANAGEMENT there are some
cases that look like:
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
DEVICE_DEFINE()
#else
DEVICE_AND_API_INIT()
#endif
There is no need to special case this as the pm_control_fn argument to
DEVICE_DEFINE will just be ignored in the
!CONFIG_DEVICE_POWER_MANAGEMENT case. So we can cleanup the code a
little and remove the #else cases for the drivers that do this.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replaces all existing variants of value clamping with the MIN and MAX
macros with the CLAMP macro.
Signed-off-by: Trond Einar Snekvik <Trond.Einar.Snekvik@nordicsemi.no>
This removes a semaphore unlock in init_spi function
which causes risks of competitive access
Signed-off-by: Clotilde Sattler <clotilde.sattler@stimio.fr>
Set stm32_dt_pinctrl_configure function as the unique entry point
to STM32 DT pinctrl management.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move pinctrl remap functions out of stm32f1 definition in order
to get it available to all series.
Allows use of more IS_ENABLED macros in calling drivers and make
code more readable.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Moved enabling SPI peripheral in front of the buffers loop.
Removed SPI DMA switching on in front of the buffers loop.
Signed-off-by: Łukasz Mazur <lukasz.mazur@hidglobal.com>
Removed SPI peripheral disabling when switching DMA to another buffer.
When using hardware chip select this would cause to stop driving
CS pin when swhitching buffers. This is different (and wrong) than
when used software CS.
Fixes#28833
Signed-off-by: Łukasz Mazur <lukasz.mazur@hidglobal.com>
Add an emulation controller which routes SPI traffic to an attached
emulator. Only one emulator is supported per bus at present, since
chip-selction functionality is not present.
This allows drivers for SPI peripherals to be tested on systems that
don't have that peripheral attached, with the emulator handling the SPI
traffic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Function spi_context_longest_current_buf() has been introduced in
commit ddef35c1da for the purpose of
getting the longest possible (potentially partial) SPI transfer
for which all currently active directions have a continuous buffer.
Such transfer can be done with taking advantage of a DMA that cannot
use scattered buffers (and this is the case for nRF SPI drivers with
which this function has been introduced).
Unfortunately, because of its inadequate name, later on this function
has been incorrectly used in other SPI drivers for getting the longer
of TX/RX buffers. And commit afc480f12b
recently "fixed" the implementation of this function, assumably to
adjust it to those incorrect uses, but this way it has also broken
the nRF SPI drivers.
Instead of restoring the original implementation of the function in
question, this commit adds a new one with functionality equivalent
to that original but with a hopefully less misleading name, and this
function is used in the nRF SPI drivers.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Enable by default the use of RAM buffers in the spi_nrfx_spim.c
driver for copying TX data located in flash (as SPIM peripherals
cannot transfer directly form flash). Without this patch, users can
get confused, especially when SPI transaction is used by an upper
level driver which does not check all error codes.
For size of the buffer, use the value used so far in the reel_board
default configuration and in the SPI loopback test, i.e. 8 bytes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
- Fix GPIO CS timing when using DMA. When using GPIO CS the
CS select was enabled after the DMA started the transfer,
resulting in the first few bits being transfered while
CS was still disabled.
- Fix TX or RX only DMA transfers. When only a RX or only
a TX transfer was requested the DMA never finished.
For the RX only cause the size on the transfer was
calculated by taking the TX buffer length (0), this
caused problems.
For the TX only transfer the RX buffer was set to NULL,
this caused the DMA to acctually writing data to the
adress 0x00000000. By using the dummy destination buffer
it now only writes to valid memory.
- Add semaphore to signal that DMA is ready, instead of
just busy waiting.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
These are all the case that coccinelle cannot find as they are inside
macro declarations.
Fixed via:
git grep -rlz -E "\(struct device \*" |
xargs -0 sed -i 's/(struct device/(const struct device/g'
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Some needed to wrap the device pointer into device's data, where others
needed only device's data to be passed to HAL callback function.
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add SPI driver for the Xilinx AXI Quad SPI IP. Despite the name, this IP
block supports both single, dual, and quad line widths.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Using SPIM_FREQUENCY_FREQUENCY_M32 to check if the device has HS-SPI and
able to use higher SPI clock than 8MHz.
Signed-off-by: Jui-Chou Chung <jui-chou.chung@nordicsemi.no>
Flexcomm's SPI SSEL (or CS) will be held until frame end.
FIFOWR[EOT] (kSPI_FrameAssert enum) is the register not set.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
To keep the bus fully loaded, the SAM0 has a fast path that recognises
special cases like TX only, RX only, or TX/RX of the same size.
Commit #ea2431f32f accidentally disabled this.
This increases the utilisation from around 30 % to around 90 % at 48
MHz.
Signed-off-by: Michael Hope <mlhx@google.com>
The SAM0 has a data register and a shift register. Data that is
written to the data register is transferred to the shift register by
the peripheral.
On the SAMD51, the CPU is fast enough that the first data write hasn't
been transferred to the shift register by the time the next data write
occurs, causing the second write to be dropped, causing the receiver
to wait forever.
Fix by spinning until the data register is empty.
Signed-off-by: Michael Hope <mlhx@google.com>
Adds optional device tree properties to set delays between spi chip
select assert/deassert and clock edges in the mcux dspi and lpspi
drivers. If these properties are not set, then the minimum supported
delays are used.
Verified that tests/drivers/spi/spi_loopback/ still passes on
mimxrt1050_evk (lpspi driver) and frdm_k64f (dspi driver).
Measured with a scope that the pcs-sck-delay and sck-pcs-delay times on
the first spi transaction in the test are reduced from 7.82 us to 20 ns
on mimxrt1050_evk.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
