This will export the stm32_clock_control_init function
to restore the clocks after the low power modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
AHB3 bus support is added for compatible series.
Additionaly, fix condition for AHB2 support and fix
formatting
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
-The STM32F410RB has no AHB2 bus so LL_AHB2_GRP1_EnableClock() and
LL_AHB2_GRP1_DisableClock() should not be called for this soc.
-The interrupt table had to be changed because of no OTG_FS_WKUP_IRQn
(no USB OTG at all).
Signed-off-by: Hans Unzner <hansunzner@gmail.com>
Convert clock_control drivers from:
DEVICE_AND_API_INIT -> DEVICE_DT_DEFINE
As part of this we also changed STM32_CLOCK_CONTROL_NAME to be based on
devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Some Clocks have ifdefs only for clock_control_on but are missing
them for clock_control_off.
Additionally return ahb_clock clock frequency for stm32g0
STM32_CLOCK_BUS_IOP in stm32_clock_control_get_subsys_rate.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
1. clock: move the call for MSI hardware auto calibration enabling
before the control of MSI enable to ensure its execution in all
cases.
2. counter: add call for MSI hardware auto calibration enabling after
the LSE enabling and after possible backup domain reset that may
clear MSIPLLEN.
Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
Assuming we stay on default Power Scale 1,
overdrive is required when System Core Clock frequency is higher
than 180MHz.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
According to RM, when increasing the CPU frequency, the new number of
wait states to the Flash latency bits must be written and verified
before modifying the CPU clock source and/or the CPU clock prescaler,
to prevent NMI to occur; when decreasing the CPU frequency, after.
Tested with STM32L462 SOC and MSI with several frequencies, both
increasing and decreasing. HSE built, not tested.
Signed-off-by: Giancarlo Stasi <giancarlo.stasi@nexxiot.com>
When MSI clock is used a source of PLL, it should be possible to
select its frequency range. Fix this.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The build infrastructure should not be adding the drivers subdirectory
to the include path. Fix the legacy uses that depended on that
addition.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The STM32G0 series of MCUs only has one APB, but two reset and clock
enable registers. Fix enabling/disabling the clock and getting the rate
for peripherals in the second register.
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
STM32 clock control subsystem allows to configure a different
frequency value for core clock (SYSCLK) and AHB clock (HCLK).
Though, it is HCLK which is used to feed Cortex Systick timer
which is used in zephyr as reference system clock.
If HCLK frequency is configured to a different value from SYSCLK
frequency, whole system is exposed to desynchro between zephyr clock
subsytem and STM32 HW configuration.
To prevent this, and until zephyr clock subsystem is changed to be
aware of this potential configuration, enforce AHB prescaler value
to 1 (which is current default value in use for all STM32 based
boards).
On STM32H7, enforce D1CPRE which fills the same role as ABH precaler.
On STM32MP1, the equivalent setting is done on A7 core, so it is
not exposed to the same issue as long as SYS_CLOCK_HW_CYCLES_PER_SEC
is set with the 'mlhclk_ck' clock frequency value. Update
matching boards documentation.
Fixes#17188
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add clock support for STM32G0X SoC series.
Signed-off-by: Philippe Retornaz <philippe@shapescale.com
Signed-off-by: Francois Ramu <francois.ramu@st.com>
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move clock_control.h to drivers/clock_control.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
soc_register.h is available in most of stm32 series.
It is sometime empty or contains includes to flash_registers.h,
which is included directly with direct reference in flash driver.
soc_register.h is also included in stm32 clock drivers, but this
driver do not use direct reference to any register anymore.
Clean up these files.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
https://github.com/zephyrproject-rtos/ci-tools/pull/65 tweaks the check
for references to undefined Kconfig symbol to whitelist anything on the
form 'CONFIG_FOO_*' (or 'CONFIG_FOO_*_...'). This is meant for #endif
comments that talk about many related symbols.
Fix two existing #endif comments to use that format, so that some
entries can be removed from the whitelist in the CI check.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Change file naming pattern from BoardNameX_ll_clock.c to
clock_BoardNameX.c
File containing LL functions will have the "_ll_" naming
scheme (such as clock_stm32_ll_common.c and .h)
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-26 02:56:20 -07:00
Renamed from drivers/clock_control/stm32_ll_clock.c (Browse further)
