-The STM32F410RB has no AHB2 bus so LL_AHB2_GRP1_EnableClock() and
LL_AHB2_GRP1_DisableClock() should not be called for this soc.
-The interrupt table had to be changed because of no OTG_FS_WKUP_IRQn
(no USB OTG at all).
Signed-off-by: Hans Unzner <hansunzner@gmail.com>
This is in order to reduce the redundancy code writing for fatal and
assert handler for error case testing. They can be used both in kernel
and userspace, and are also SMP safe.
Signed-off-by: Enjia Mai <enjiax.mai@intel.com>
Conditionally use either DPPI or PPI channel in the sample so that
it can be built for all nRF SoCs. Update documentation accordingly.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
`delta_size` was incorrectly used to assess whether extended option
length field shall be used. In result, options larger than 268 bytes
were not encoded properly.
Fixes#31206
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
As recommended by @mbolivar-nordic and... stackoverflow.
While I could not reproduce this locally, this should get rid of many
non-fatal pip errors in CI all looking like this one:
Building wheels for collected packages: PyYAML, progress, psutil, ...
Running setup.py bdist_wheel for PyYAML: started
Running setup.py bdist_wheel for PyYAML: finished with status 'error'
Complete output from command /usr/bin/python3 -u -c "import setuptools,
tokenize;__file__='/tmp/pip-build-b3sj5a6m/PyYAML/setup.py';
f=getattr(tokenize, 'open',open)(__file__);code=f.read().replace(
'\r\n', '\n');f.close();exec(compile(code, __file__, 'exec'))"
bdist_wheel -d /tmp/tmpvn0bt6xfpip-wheel- --python-tag cp36:
Failed building wheel for PyYAML
usage: -c [global_opts] cmd1 [cmd1_opts] [cmd2 [cmd2_opts] ...]
or: -c --help [cmd1 cmd2 ...]
or: -c --help-commands
or: -c cmd --help
error: invalid command 'bdist_wheel'
----------------------------------------
Running setup.py clean for PyYAML
Etc.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
junitparser version 2 is incompatible with check_compliance.py, it fails
like this:
File "./scripts/ci/check_compliance.py", line 295, in parse_kconfig
self.skip("Not a Zephyr tree (ZEPHYR_BASE unset)")
File "./scripts/ci/check_compliance.py", line 141, in skip
self.case.result = Skipped(msg, "skipped")
File "/usr/local/lib/python3.9/site-packages/junitparser/junitparser.py"
line 682, in result
for entry in value:
TypeError: 'Skipped' object is not iterable
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Likely an accident when commit 288ae28c13 moved the script to the main
repo. Stayed unnoticed because this handler rarely ever runs.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Replace these with links to the actual documentation as needed, or
just remove them entirely. These are getting copy/pasted around and
I'm trying to avoid that happening in the future.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Add check that validates that the base addresses specified in DT nodes
representing the ECB peripheral match the addresses of that peripheral
defined in MDK.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Convert the driver so that it creates its instance basing on DT.
Remove no longer needed Kconfig option CRYPTO_NRF_ECB_NAME.
Also update accordingly the crypto sample.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add binding for the Nordic ECB (AES electronic codebook mode
encryption) peripheral and corresponding devicetree nodes for
nRF SoCs that feature this peripheral.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Since MDK was updated and now it contains the definition of QDEC
peripheral for nRF52805, the DT node representing this peripheral
can be processed normally.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Since the PU power rail of i2c bus might be gone at the initial state
after ec powered up, we might have no chance to get STOP condition. This
is because no i2c transactions occurred before its power rail is
restored. But it's crucial to reset the whole i2c module after i2c bus
is back to the idle state.
The original test suite for i2c recovery mechanism didn't consider this
case that initial i2c bus is low before ec powered on. Hence, this CL
fixed this symptom by:
1. Force i2c modules must proceed 'reset' step no matter we received
STOP condition or not.
2. Use Boolean for condition check to prevent misusage and meet MISRA.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
- Use older junitparser, new version is not compatible
- Fetch pull request ref, not master
- add few debug messages
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Looks like those two SoCs still had old header information depending on
Kconfig from SOF, remove those and set trace size directly.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Extend the PWM API with optional API functions for capturing PWM pulse
width and period cycles.
Fixes#26026.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Document the use of DEVICE_DT_GET() to fetch device pointers at
compile time, and update the documentation on defining device
instances to use the devicetree macros.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Mark the CANopen sample with program download support as build-only
since it depends on MCUboot being flashed to the board prior to the
generated application firmware image.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
All other silabs_exx32 socs already have this change applied, only
efr32bg13p was missing. This is now done, so all silabs_exx32 are
similar.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
* add toolchain abstraction for coverage
* add select HAS_COVERAGE_SUPPORT to kconfig
* port gcov linker code to CKake for arc
* give user permission to gcov bss section
* expand the size of iccm and dccm to 1M
Signed-off-by: Jingru Wang <jingru@synopsys.com>
Before hooking up the MMU driver code to the Zephyr MMU core code it's
better to match the expected variable types of the two parts.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The MMU code is currently assuming that Zephyr only uses one single set
of page tables shared by kernel and user threads. This could possibly be
not longer true in the future when multiple set of page tables can be
present and swapped at run-time.
With this patch a new arm_mmu_ptables struct is introduced that is used
to host a buffer pointing to the memory region containing the page
tables and the helper variables used to manage the page tables. This new
struct is then used by the ARM64 MMU code instead of assuming that the
kernel page tables are the only ones present.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The ARM64 MMU code used to create the page tables is strictly tied to
the custom arm_mmu_region struct. To be able to hook up this code to the
Zephyr MMU APIs we need to make it more generic.
This patch makes the mapping function more generic and creates a new
helper function add_arm_mmu_region() to map the regions defined by the
old arm_mmu_region structs using this new generic function.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
In the current code the base xlat table is a standalone array. This is
done because we know at compile time the size of this table so we can
allocate the correct size and save a bit of memory. All the other xlat
tables are statically allocated in a different array with full size.
With this patch we move all the page tables in one single array,
including the base table. This is probably going to waste a bit of space
but it makes easier to:
- have all the page tables mapped in one single contiguous memory region
instead of having to take care of two different arrays in two
different locations
- duplicate the page tables more quickly if we need to
- use a pre-allocated space to host the page tables
- use a pre-computed set of page tables saved in a contiguous memory
region
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
MESH/NODE/CFG/HBS/BV-01-C expects the MinHops to be 0x7f after
disabling subscription, but 0x00 for subsequent Get requests.
MESH/NODE/CFG/HBS/BV-02-C expects us to return previous
count value and then reset it to 0.
Signed-off-by: Michał Narajowski <michal.narajowski@codecoup.pl>
Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3
is used as a clock source by certain peripherals, e.g. LTDC.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
