The toolchain headers included an abstraction for defining symbol
names in assembly context in the situation where we're using a
DOS-style assembler that automatically prepends an underscore to
symbol names.
We aren't. Zephyr is an ELF platform. None of our toolchains do
this. Nothing sets the "TOOL_PREPENDS_UNDERSCORE" macro from within
the project, and it surely isn't an industry standard. Yank it out.
Now we can write assembler labels in natural syntax, and a few other
things fall out to simplify too.
(NOTE: these headers contain assembly code and will fail checkpatch.
That is an expected false positive.)
Change-Id: Ic89e74422b52fe50b3b7306a0347d7a560259581
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Completing the terminology change started with change 4008
by updating the Kconfig files processed to produce the
online documentation, plus header files processed by
doxygen. References to 'platform' are change to 'board'
Change-Id: Id0ed3dc1439a0ea0a4bd19d4904889cf79bec33e
Jira: ZEP-534
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Add a Kconfig option to select between the Hard and Soft Float ABIs. We
also default to the Hard Float ABI as this is what older SDK versions
supported.
JIRA: ZEP-555
Change-Id: I2180c98cd7556ab49f5ca9b46b31add2c11bd07b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Arches now select whether they want to use the GCC built-ins,
their own assembly implementation, or the generic C code.
At the moment, the SDK compilers only support builtins for ARM
and X86. ZEP-557 opened to investigate further.
Change-Id: I53e411b4967d87f737338379bd482bd653f19422
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Used by ARC, ARM, Nios II. x86 has alternate code done in assembly.
Linker scripts had some alarming comments about data/BSS overlap,
but the beginning of BSS is aligned so this can't happen even if
the end of data isn't.
The common code doesn't use fake pointer values for the number of
words in these sections, don't compute or export them.
Change-Id: I4291c2a6d0222d0a3e95c140deae7539ebab3cc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Adds Kconfig options CPU_HAS_FPU, FLOAT and FP_SHARING for the arm
architecture.
NOTE: All SOCs in the MK64F12 family have an FPU so that makes it a
convenient location to enable the hidden CPU_HAS_FPU option.
Change-Id: I71771d24f20f52079314bb8db9bf8a0aa827ab41
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Enable floating point in the Cortex-M4 processor.
Change-Id: Ibadae12b9197d6486fd5c6a3d4e177fa9e1c71bc
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Saves and loads the non-volatile FP registers (s16-s31) when switching
between threads.
Change-Id: Ib3190452d9a70d722032ac83176eb4fbb92aca3d
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds the preemptive floating point registers to the ARM's thread
control structure.
Change-Id: I65fbee6303091ce0658bbc442c4707d306b68e92
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Updates the exception stack frame structure to include floating point
registers.
Change-Id: I0fef784cf4d91dda245180abd75bfd9221825fba
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The ReST parser dislikes enumerations with no empty lines in
between. Whatever.
Change-Id: I480c08fe5b69f0d0f3ebfacdc64fc9e3ec94da21
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
Fibers initialize this back pointer to NULL as they are (by definition)
not microkernel tasks. Microkernel tasks initialize it to their
corresponding 'ktask_t'.
However for nanokernel systems, the back pointer is always NULL. This
is because there is only one task in a nanokernel system (the background
task) and it can not pend on a nanokernel object--it must poll.
Change-Id: I9840fecc44224bef63d09d587d703720cf33ad57
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
We really should have more faith in the compiler, it generates
code to implement this exactly like the arch-specific assembly
versions, and on ARM is actually 4 bytes shorter.
FUNC_NO_FP used to disable the usual C preamble to update the
frame/stack pointers, which is how the sizes are still the same
or less. It's debatable how useful the occasional use of
FUNC_NO_FP is in practice since it hinders debugging and in a
production build frame pointers should be globally disabled, but
we can address that later.
Change-Id: I6c4b64ab3e3a9b6f91d52fa8c92e6e79a986fc77
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Of the 3 related functions;
_thread_essential_set()
_thread_essential_clear()
_is_thread_essential()
The first two are parameter-less and always operate on
"_nanokernel.current". The last one takes a 'thread' parameter but will
operate on _nanokernel.current if the parameter is NULL. All calls to
_is_thread_essential() pass NULL!
This change makes the 3 functions consistent by removing the parameter
to the 3rd function. This should also be marginally more efficient,
though consistency was the motivation. This change corrects the doc
preamble to all 3 functions.
(These functions would probably be better as inlines. Also, the choice
of when to use wrappers seems a bit arbitrary. E.g. there's nothing
for setting/testing the "FIBER" flag.)
Change-Id: Ie3589f8a28b227c6d7a3a31b664d3b3e6e9c6d17
Signed-off-by: Geoff Thorpe <geoff.thorpe@nxp.com>
Use SOC_FAMILY and SOC_SERIES to identify soc families and series
and to point to the correct linker files and files related to a
specific SoC.
Change-Id: I8b1a7339f37d6ea4161d03073d36557a40c0b4a6
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
GCC enables unaligned memory access for ARMv6 and above.
Once unaligned memory access is allowed, there's no need
for the unaligned memory access trap.
The change prevents the situation when the compiler
generates code that uses unaligned memory access, but
the CPU generates an exception when this code runs.
Change-Id: Id33f2264c631772e5c561e76fb579d8b7bc26e1e
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Changed names of Kconfig flags, variables, functions, files and
return codes consistent with names used in the RFC. Updated
relevant comments to match the changes.
Origin: Original
Change-Id: Ie7941032d7ad7af61fc02928f74538745e7966e8
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Use of `ldr` triggers unaligned memory access when loading SVC
instruction to r0. This is caused by the fact that SVC is a 16-bit
instruction, hence with a 2 byte offset, we are performing an non-word
aligned access. Prevent this by using `ldrh` to load a halfwords rather
than full words.
Change-Id: Ieae60c2ce86c6cfe15c89627d3a450797ce7e714
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Make kconfig look the same for all architectures.
JIRA: ZEP-107
Change-Id: Ia8100194ec333fc07a1dff4f6f90364ce8bef4d3
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The nmi_on_reset.S functions are used by all ARM platforms. It
makes no sense to repeat the same code for all platforms. Moving
the code from each SOC implementation to arch/arm/core.
The same treatment for the NMI_INIT() macro. Moving it from a per
SOC implementation to the include/arch/arm/cortex_m/nmi.h.
Change-Id: I574d8880a44046cc7b9e1b635e80d6e83657b8c1
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
The thread monitor allows to iterate over the thread context
structures for each existing thread (fiber/task) in the system.
Thread context structures do not expose thread entry information
directly. Although all the information can be scavenged from memory
stacks. Besides, accessing the information depends on the stack
implementation for each architecture.
By extending the tcs we allow a direct access to the thread
entry point and its parameters, only when thread monitor is
enabled.
It also allows a task to access its kernel task structure
through the first parameter of the thread.
This allows a debugger application to access the information directly
from the thread context structures list.
Change-Id: I0a435942b80eddffdf405016ac4056eb7aa1239c
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@intel.com>
This table was still being added to ROM even if
CONFIG_SW_ISR_TABLE=n.
Change-Id: Ia0de1349960af1c62e88344b3d5b6655b638219b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This config option is no longer implemented and doesn't actually
do anything.
Change-Id: I57ab7ba688f57da21f8a58f62ea37dc6b8daaf18
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We don't support hard-coding vectors in this table anymore.
If someone really wants to do this, they can set
IRQ_VECTOR_TABLE_CUSTOM and define their own.
Change-Id: I45f49782ba5fefb0a02eab02ec96efd0019bc6d5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This patch updates some help sections to remove the "ERROR:
Unexpected indentation" messages during hmtl documentation
generation.
Change-Id: Idcdc17727b921b6145f9eb28d85975ceca273ce2
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
The app-facing interface for configuring interrupts was never
formally defined, instead it was defined separately for each arch
in their respective arch-specific header files. Occasionally these
would go out of sync.
Now there is a single irq.h header which defines this interface.
To avoid runtime overhead, these map to _arch_* implementations of
each that must be defined in headers pulled in by arch/cpu.h.
Change-Id: I69afbeff31fd07f981b5b291f3c427296b00a4ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We have a new policy: users should not be able to configure
an interrupt with "forbidden" priority levels, and any priority
levels with special semantics will be activated by flags.
Change-Id: I757c19cfedcb1d0938eaf4da348ddafb71b3e001
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This simulates a reboot by jumping back to the address stored in the
reset vector in vector table found at address 0. It is supported from
interrupt/exception level, which means that sys_arch_reboot() in this
case finds out if it is called from thread mode or handler mode, and in
the latter case, it unwinds the nested exception stack as needed.
Change-Id: Ib67f850f8411f1ee8fc592a5f31f2f70d0af14a4
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The bootloader expects the entry point to be called __start, not __reset.
Change-Id: I5a5f7f45c248b9398e58fb026c731f8617fe4856
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Add sys_exc_connect() (and its x86-compatible alias nanoCpuExcConnect())
that allows connecting an exception handler at runtime.
The current implementation is a bit of a bastard, to avoid disturbing
the current implementation of the exception handlers. Instead of hooking
_exc_wrapper() in all vectors and adapting the exception handlers, the
current exception handlers are still hooked directly in the vectors.
When an exception is hooked at runtime, _exc_wrapper() gets installed in
the vector and the real handler gets inserted in _sw_exc_table; this
means that the scheme only works with non-XIP kernels.
This should be enhanced so that _exc_wrapper() is hooked in all vectors,
and that current exception handlers (for faults mostly) are reworked to
be inserted in the _sw_exc_table and wrapped in _exc_wrapper().
Change-Id: Icaa14f4835b57873d2905b7fbcbb94eeb3b247d1
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
For non-XIP systems, it's not in ROM, so remove the "ROM" part. Adapt it
to coding conventions at the same time, and export it to C code.
Change-Id: Id09a6be8bc9c462667ed71b53be7fa5382c88db3
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Find out on which stack the stack frame for an exception is in the assembly
code (__fault()) rather than in C (_Fault()). This will allow pushing
more registers on the stack when debugging is enabled.
Change-Id: I1c510b83098536f8930392b17df27511ccd04d80
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename the function and allow it to handle the 'type'
argument, which is ignored in this case.
Change-Id: I3d3493bea4511b2d026747505e7e52c5acc85012
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The ESF was built using the 'alias' names of the GPRs (a1, lr, pc, etc)
rather than their 'real' name (rN).
Change-Id: I49cae5e94869a79a3165dc7f2347d8cec39dbf67
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The processor is made aware that the vector table built in the image is
located at the start of SRAM in the case of a non-XIP image, rather than
at 0 in as is the case in XIP images.
Change-Id: I40b28ca32daf3e8930f103224766ed4e0ccc88e0
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Adds C++ support to the build system.
Change-Id: Ice1e57a13598e7a48b0bf3298fc318f4ce012ee6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds extern "C" { } blocks to header files so that they can be
safely used by C++ source files.
Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
We can save a great deal of RAM this way, it only needs to be
in RAM if dynamic interrupts are in use.
At some point this config option broke, probably when static
interrupts were introduced into the system.
To induce build (instead of runtime) errors when irq_connect_dynamic()
is used without putting the table in RAM, the dynamic interrupt
functions are now conditionally compiled.
Change-Id: I4860508746fd375d189390163876c59b6c544c9a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This removes the default flash and SRAM base addresses from the ARM core
Kconfig file. Each individual SoC/processors Kconfig has to define them.
This is in preparation to support Atmel SAM3 family processors as they
have different base addresses.
Change-Id: I97ea9b43386d1e286ee692f583c97cfbb5399b0f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The interrupt API has been redesigned:
- irq_connect() for dynamic interrupts renamed to irq_connect_dynamic().
It will be used in situations where the new static irq_connect()
won't work, i.e. the value of arguments can't be computed at build time
- a new API for static interrupts replaces irq_connect(). it is used
exactly the same way as its dynamic counterpart. The old static irq
macros will be removed
- Separate stub assembly files are no longer needed as the stubs are now
generated inline with irq_connect()
ReST documentation updated for the changed API. Some detail about the
IDT in ROM added, and an oblique reference to the internal-only
_irq_handler_set() API removed; we don't talk about internal APIs in
the official documentation.
Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Changes the nanokernel stack API so that the timeout parameter must be
specified when invoking nano_isr_stack_pop(), nano_fiber_stack_pop(),
nano_task_stack_pop() and nano_stack_pop().
This obsoletes the following APIs:
nano_fiber_stack_pop_wait()
nano_task_stack_pop_wait()
nano_stack_pop_wait()
Note that even though the new API requires that the timeout parameter
be specified, there are currently only two acceptable values:
TICKS_NONE and TICKS_UNLIMITED
This nanokernel option does not support CONFIG_NANO_TIMEOUTS.
Change-Id: Ic7f16ee30c3534115ceffa19ef8591ecc5a79080
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel LIFO API so that the timeout parameter must be
specified when invoking nano_isr_lifo_get(), nano_fiber_lifo_get(),
nano_task_lifo_get() and nano_lifo_get().
This obsoletes the following APIs:
nano_fiber_lifo_get_wait()
nano_fiber_lifo_get_wait_timeout()
nano_task_lifo_get_wait()
nano_task_lifo_get_wait_timeout()
nano_lifo_get_wait()
nano_lifo_get_wait_timeout()
Change-Id: Ie9f93e46da42ea33c32544c02ab1d70b893cc198
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel semaphore API so that the timeout parameter must be
specified when invoking nano_isr_sem_take(), nano_fiber_sem_take(),
nano_task_sem_take() and nano_sem_take().
This obsoletes the following APIs:
nano_fiber_sem_take_wait()
nano_fiber_sem_take_wait_timeout()
nano_task_sem_take_wait()
nano_task_sem_take_wait_timeout()
nano_sem_take_wait()
nano_sem_take_wait_timeout()
Change-Id: If7a4bce1bd8ec8d6410d04f3c16ff1922ff0910e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel FIFO API so that the timeout parameter must be
specified when invoking nano_isr_fifo_get(), nano_fiber_fifo_get(),
nano_task_fifo_get() and nano_fifo_get().
This obsoletes the following APIs:
nano_fiber_fifo_get_wait()
nano_fiber_fifo_get_wait_timeout()
nano_task_fifo_get_wait()
nano_task_fifo_get_wait_timeout()
nano_fifo_get_wait()
nano_fifo_get_wait_timeout()
Change-Id: Icbd2909292f1ced0bad8a70a075478536a141ef2
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Causes problems for large values of CONFIG_NUM_IRQS.
Some inconsistencies have been noted in how CONFIG_NUM_IRQS is
used on these platforms, with bugs filed. This patch preserves
existing behavior and has been shown to generate the same number
of table entries for both arches using objdump.
Change-Id: I1d3ac5466978acb56e88a6dc3cbe7cc09431e94d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
