sometimes there are some unencodable unicode chars from output
of west flash command, need to ignore them rather than reporting
an error.
Signed-off-by: Chen Peng1 <peng1.chen@intel.com>
MIPS architecture support was introduced
in 0369998e61 ('arch: add MIPS architecture support').
Also sort supported architectures list alphabetically.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
The stress ('scuse me, "zstress") cases here are all written to
exercise reader/writer threads at different priority combinations.
That's defeated if the threads are allowed to run on different CPUs
(because being "low" priority doesn't matter if you have a spare CPU
to run on).
There is also extensive use of stack buffers to pass data through the
ring buffer zero copy implementation, which runs afoul of the
KERNEL_COHERENCE rules on intel_adsp platforms (where stack memory is
incoherent between CPUs and can't be shared like that).
Fix both issues by just setting CONFIG_MP_NUM_CPUS=1
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This platform was stale for a long time and got a little left behind.
Basic OS stuff was working but secondary core bringup didn't. It has
a slightly different set of choices from the "weird hardware
quirks" menu:
+ Like cAVS 1.5, it boots from a ROM that needs a short delay after
power-up before it can receive the startup IDC.
+ But, like 2.5 and unlike 1.5, it doesn't start running until the
PWRCTL bit for the core gets set by DSP software (1.5 gets launched
by the host). So the delay needed to move down a bit.
+ It wants that PWRCTL bit to be set last, after CLKCTL enables the
clock. (Which makes sense I guess: EE classes always tell you hold
circuits in reset while an initial clock propagates). Not sure why
it was in the reverse order originally; this way works for
everything.
+ The ROM likes to scribble on the interrupt controller and mask its
own IDC interrupts after we've already set it up. They have to be
unmasked. We had code to do this already, thinking it was a
workaround for legecy SOF code (that we never actually located).
Now I'm thinking it was this behavior all along being detected by
SOF's more extensive hardware CI. Take out the test and do it
always, it's like nine instructions.
+ The host/loader-side behavior is a mix of 1.5 and 2.5. It won't
actually start the secondary cores under host command, but it does
need to see bits set for them in ADSPCS for the DSP-initiated
power-up to work (2.5 would just ignore all but core 0's bits).
+ Also, like 1.5, it needs the host DMA stream to be explicitly
stopped (and not just reset) or else further loads will be unstable.
Note that the loader changes now require more logic than just "1.5 or
not", so the platform detection has been enhanced to fully categorize
the device based on PCI ID (not quite: we don't have any 2.0 platform
hardware, so I left that alone for now).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
CONFIG_OPENOCD_SUPPORT was deprecated in favor of
CONFIG_DEBUG_THREAD_INFO in Zephyr v2.6.0 and can now be removed.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Let's have dev_data for dev->data so it will not conflict with struct
call_back data variable.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit adds support for adjust the addresses of the final image.
This is useful when the image is to be flashed at a location different
from the LMA address encoded in the ELF file by the linker.
An example use-case is multicore systems where core A might load image
from a flash partition into RAM in order for core B to execute and load,
but where the image itself is build with the RAM addresses as LMA.
It updates the zephyr_image_info.h header with information of adjustment
value.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit adds the `gen_image_info.py` script which supports creation
of a header file with image information from the EFL file.
This version populates the header file with:
- Number of segments in the image
- LMA address of each segment
- VMA address of each segment
- Size of each segment
The header file can be used by a secondary build system which needs this
information.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Coverity identified valid error where the routine does a NULL
check for two different pointers after they have been dereferenced.
fixes#39868fixes#39874
Signed-off-by: David Leach <david.leach@nxp.com>
Conceptually the net_mgmt_lock should be a mutex instead of a
semaphore. It is easier to identify the owner of a mutex and
debug when deadlock happens, so convert it.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
This configures soc and flash size definition
using DTSI information instead of hardcoded
values.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This modifies esp32c3 SOC configuration to support MCUBoot.
CmakeLists is moved from board to soc specific. It also
includes MCUBoot changes.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This change creates XiP image handling and proper
LMA and VMA regions configurations.
This also adds common-ram.ld and common-rom.ld sections that
require explicit handling due to image sections limitation
in esptool.
Move additional drivers into IRAM to protect against
flash cache disable read/write operation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Calling gettimeofday() from _gettimeofday() in a non-Posix build
environment can result in a recursive call loop, causing a stack
overflow. Modify _gettimeofday() to return -1 for non-posix systems
(the previous behaviour that was added in #22508).
Fixes#41095
Signed-off-by: Binu Jacob <bjj@planetinnovation.com.au>
Current version of STM32 PTP clock reads current PTP time by querying
second and nanosecond registers sequentially. It is possible for second
to roll over between reading second and nanosecond registers, causing
returned time to be off by a second. This bugfix resolves that issue.
Signed-off-by: Alex Sergeev <asergeev@carbonrobotics.com>
There's desire for a "log only" mode like the older adsplog script
had. Add a few other quality of life command line options too. And
catch the most obvious user errors to print a message instead of a
stack dump.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There were several generations of loader/logger tooling in this
directory, several of which no longer work. They have all been
replaced by just one pythong script in the soc directory.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This is based closely on the older cavsload.sh script, but updated to
keep up with interesting new twister behavior, with a cleaner
interface for CI integration that doesn't require editing the file,
somewhat better internal documentation, and with a more focused eye on
use as a twister tool specifically.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The existing scripting for these platforms has gotten a little stale.
The loader had bifurcated into a v15 and v25 variant, both of which
lived in the cavs15 board directory. Building off Shao Ming's
excellent (if somewhat surprisingly committed) rework to unify
unchanged parts of the scripts, let's finish the job.
This adds a "cavstool.py" script with the following advantages:
+ It's just one script for everything, with a single unified load
process that works reliably on both 1.5 and 1.8+ hardware.
+ It runs on all cAVS platforms (with a compatible kernel, those
requirements haven't changed)
+ It automatically emitts logging synchronously after loading,
eliminating the race between adsplog.py and cavs-fw.py where you
could see logging from a previous test run.
+ It automatically detects and unloads a linux kernel module managing
the same device (even if SOF has renamed the module again, heh).
+ Timings have been tuned up in general, it's about 2 seconds faster
to get to first log output now.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Adds initial GATT BSIM tests for the client
and server functionality, testing simple
reads and writes.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
For tracing_user, the sys_trace_isr_enter() & sys_trace_isr_exit()
block any nest interrupts & most SMP interrupts for the user. It is
hard to analyze the IRQ preemption(e.g., each IRQ counter and execution
time). This commit adds ISR nest level for each CPU to the user instead
of blocking user call back when nest interrupts.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Remove the only_tags filter for the board and add ignore_tags for net
and bt.
Adds a filter to a userspace sample that didn't correctly filter on
usermode being Kconfiged.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Document the existance of `zephyr.tag` by providing a link on the main
documentation guide page. Also include an example of how to use this
file in an external project.
Implements #41529.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Generate the Doxygen tag file to static html sources directory so that
external documentation can use it as a source for linking. See:
https://www.doxygen.nl/manual/external.html
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Exposes the RC register so that the initial value can be set in
the device tree. This is useful in the case where the timer
generates an event but an interrupt is not required.
e.g generate event to sample adc on RC register match.
Tested on Atmel SMART SAM E70 Xplained Ultra board
Signed-off-by: Marius Scholtz <mariuss@ricelectronics.com>
Add a check for SDU size and tx qos to ensure that we do not
attempt to send any data and neither central or peripheral
if the benchmark has been setup to be rx-only.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
This test is triggering some kind of bug that will reliably cause a
full host crash/hang of the x86 host environment on TGL/cAVS 2.5.
It's interfering with CI testing, so filter it out for now while we
figure it out.
Interestingly it doesn't have any trouble on older cavs15. And even
more so, it seems to be some kind of build interaction. If I disable
LOG=y, it passes. But when it fails, it actually fails BEFORE the boot
entry and core 0 initialization code is reached (i.e. LONG before any
logging initialization). Something is wrong with the generated file;
maybe a linker or rimage bug? The signature is reported OK by the
ROM, but that's the last we hear from the device before it blows up.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The test_queue_multithread_competition case wants to be sure that an
inserted item is recevied by the highest priority thread of several
waiting, but that only works if the threads aren't racing against each
other on different CPUs.
Also, the test_queue_loop case would produce a LOT of console output
very quickly. On a few occasions, I saw this overflow the 8k output
buffer of the intel_adsp devices at exactly the wrong time (with
respect to the polling loop in the host python script), cause a flush
of the stream, and then miss the SUCCESSFUL message. Quiet things
down a bit, there's not a lot of value of verbosity in a CI test.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These two cases use a k_pipe to transfer data, and do it (as is
customary) by copying into or out of buffers on the stack. But that
doesn't work when KERNEL_COHERENCE=y, because the pipe code has a
possibly-too-sophisticated zero copy implementation, and will do the
copy into the destination thread synchronously with the k_put_put()
call from the other CPU.
Normally the fix is to use a static buffer instead, but in this case
the buffers are shared between multiple simultaneous threads, so can't
be shared.
Just skip the tests, pending some rework to how they communicate.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This is test assumes that shared static/global variables are coherent
between the CPUs. That's true on incoherent platforms only when
CONFIG_KERNEL_COHERENCE=y. Normally that gets turned on along with
SMP, but this is using the lower level mp API directly and didn't have
that.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The commit fixes bug in compile time calculation of file download
chunk, FS_MGMT_DL_CHUNK_SIZE, that is permitted within selected
mcumgr buffer size, where the mcumgr header length has not been
taken into account.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Instead of redefining own `struct zsock_timeval` type at the socket
layer, use a standard type provided by libc. This prevents the
compliation errors when application includes both, `net/socket.h` and
standard C header defining `struct timeval` (sys/time.h).
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Current gpio and uart initialization level is set to
PRE_KERNEL_2, which won't let uart_console subsystem
to init its hook properly as it has same level.
Prioritize uart and gpio so that the console hooks
are properly initialized.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Current uart driver implementation is incompleted regarding the
usage of DT_INST_FOREACH_STATUS_OKAY. If uart0 and uart2 are selected,
build breaks due to peripheral number ordering, which would be
0 and 1 in this case. This fix PR fix this by re-working the macros
and setting proper uart peripheral instances in DTSI, required for signal
routing configuration.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Periodic advertising synchronization create had a timeout set
to fixed value of 10 seconds. BT 5.3 Core specification defines
synchronization timeout as 6 consecutive periodic advertising
events. When advertiser set the periodic interval to be more than
1.6 second it was possible the application timeout is reached
before time allowed by BT Core specification.
Changed implementation of timeout to depend on the periodic
advertising interval.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
