Commit graph

9 commits

Author SHA1 Message Date
Andrew Boie
738dec483e nios2: add static interrupt handling code
Supports Internal Interrupt Controller only for now; EIC
supoort tracked in ZEP-258.

Change-Id: I2d9c5180e61c06b377fce4bda8a59042b68d58f2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 16:42:21 +00:00
Andrew Boie
e2ff2fdd91 nios2: add base exception handling code
Change-Id: I56b0ec1a3576a77ca7bd6f2c0217de8053406927
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 16:42:20 +00:00
Andrew Boie
7bd697b0d5 nios2: add _nios2_reg_write/read functions
The technical manuals and example HAL code frequently refer to
register bank numbers from some base address. Add these helper
functions to read and write registers correctly using this
notation.

Change-Id: Ia082f5cc89081fcea2cb6ad8204c1b9b2650d3fd
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-22 16:42:19 +00:00
Andrew Boie
01724d319d nios2.h: cleanup API
This header was pulled in verbatim from Altera HAL and had
some style and naming issues. The inline functions or macros
which read registers can now be used in expressions.

Change-Id: I7a463717051efd2f9dd36e8a84d357852fbf9215
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-06-10 15:22:41 +00:00
Andrew Boie
7ff96dc4a4 nios2: implement _arch_irq_lock / unlock
Change-Id: I16fd64577f45db9531dd0d472279c255c5b8ff13
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-09 18:09:29 +00:00
Andrew Boie
cfe645cef3 nios2: add config-independent CPU defines
This file is taken verbatim from the Altera Nios II HAL
source and includes various useful processor defines
and macros.

Change-Id: Idbf0b49bebe33bb5a53f5155d927bafadda9a2fe
Origin: nios2.h Altera Nios II HAL
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-09 18:09:28 +00:00
Andrew Boie
8564875a98 nios2: provide and include soc-specific headers
BSP builds for Nios II generate a linker.h and system.h which reflects
the configuration for that CPU. This can vary depending on how the CPU
is wired up in QSYS, so it needs to be at the SOC level--we essentially
treat any given CPU configuration as a SOC in Zephyr build terms.

Include these files from <arch/cpu.h>.

Change-Id: I12f76600107fec1a14a2f9cb82b0f55915ec03a6
Origin: Altera Quartus tools, machine generated
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-09 18:09:28 +00:00
Andrew Boie
7f7337a0fe nios2: fatal: add _SysFatalErrorHandler and _Fault stub
ZEP-252 will handle implementation of the code here.

Change-Id: I3e9a6c7cdf2d5a3b0240317b772628fead528095
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-09 18:09:27 +00:00
Andrew Boie
9433895954 nios2: basic build, non-functional
Basic build framework for Nios2. Everything is stubbed out,
we just want to have a build going so that we can start to
parallelize implementation tasks.

This patch is not intended to be functional, but should be
able to produce a binary for all the nanokernel-based
sanity checks.

Change-Id: I12dd8ca4a2273f7662bee46175822c9bbd99202a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-03 23:18:45 +00:00