Commit graph

116624 commits

Author SHA1 Message Date
Richard Skriwanek
870703fe85 samples: circular_dma: fix DMA config for nucleo_c031c6
The circular DMA sample incorrectly configured channel 3 for the
NUCLEO-C031C6 board, but this MCU has only 3 channels (0 - 2).
Fixed by changing to channel 2.

Signed-off-by: Richard Skriwanek <richy@fnc.at>
2025-06-06 14:48:24 +01:00
Shan Pen
b194050402 boards: fk743m5: add pyocd runer support
add pyocd support and fix debug section in doc

Signed-off-by: Shan Pen <bricle031@gmail.com>
2025-06-06 14:48:13 +01:00
Shan Pen
0b65f62ddb boards: fk743m5: add sdram support
add sdram support, tested with tests/drivers/memc/ram

Signed-off-by: Shan Pen <bricle031@gmail.com>
2025-06-06 14:48:13 +01:00
45e55d639d drivers: pwm: fix an off-by-one error in the CH32V PWM driver
The period is the reload register plus 1. Adjust. Note that the
earlier code handles the cases where the pulse time is zero or equal
to the period.

Signed-off-by: Michael Hope <michaelh@juju.nz>
2025-06-06 14:48:00 +01:00
Qiang Zhao
ace509fc38 west.yml: update hal_nxp
- Fix Frequency adjust issue for NETC PTP CLOCK

Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
2025-06-06 14:47:53 +01:00
Qiang Zhao
e5513ab18b dts: arm: nxp_imx95_m7: add ptp_clock node
Added ptp_clock node on imx95 core m7

Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
2025-06-06 14:47:53 +01:00
Qiang Zhao
59ae9c19de dts: bindings: Add NXP NETC PTP binding
Add binding for NXP NETC PTP Clock device

Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
2025-06-06 14:47:53 +01:00
Qiang Zhao
ac5bae59ab drivers: ptp_clock: Add NXP NETC PTP Clock Driver
Add Driver for NXP NETC PTP Clock device

Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
2025-06-06 14:47:53 +01:00
Adam Mitchell
f70485f088 dts: arm: st: h7: Correct dma-request value for H743 DMAMUX2
Reduces value of dma-requests to 12 as specified in RM0433

Signed-off-by: Adam Mitchell <adam.mitchell@brillpower.com>
2025-06-06 12:03:37 +02:00
Alvis Sun
9f1935923b driver: serial: npcx: add PM support for npck3 series.
This commit adds power management support to the UART driver for npck3
series chip.

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2025-06-06 12:03:25 +02:00
Alvis Sun
bf0fd155ae drivers: serial: npcx: add serial driver support for npck3
This commit adds serial driver support for npck3.

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2025-06-06 12:03:25 +02:00
Bjarki Arge Andreasen
d9cbd4ae1d drivers: gpio: smartbond: fix PM_DEVICE_DEFINE usage
The gpio_smartbond driver incorrectly uses the static
PM_DEVICE_DEFINE() and PM_DEVICE_GET() macros when creating a driver
instance from a devicetree instance number.

Update to use PM_DEVICE_DT_INST_DEFINE() and
PM_DEVICE_DT_INST_GET() macros.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
2025-06-06 11:52:50 +02:00
Andreas Schuster
3060ee2c5c samples: boards: add nucleo_g0b1re board with mco output
Add overlay file to enable the MCO1&2 output clock on the nucleo_g0b1re.

Signed-off-by: Andreas Schuster <andreas.schuster@schuam.de>
2025-06-06 11:52:40 +02:00
Andreas Schuster
81049c5b75 dts: arm: stm32g0: add mcos node
The newly added mcos node contains two childreen `mco1` and `mco2` that can
be used to output different clocks on the MCO pins of the stm32g0
microcontrollers.

Signed-off-by: Andreas Schuster <andreas.schuster@schuam.de>
2025-06-06 11:52:40 +02:00
Andreas Schuster
41c6257046 include: dt-bindings: stm32g0_clock: add mco macros
Adds macros to be able to use the microcontroller clock output (MCO) on the
STM32G0 microcontroller.

Signed-off-by: Andreas Schuster <andreas.schuster@schuam.de>
2025-06-06 11:52:40 +02:00
Luca Burelli
8e765b78a2 cmake: add_llext_target: fix command expansion
This fixes the invocation of the 'elfconvert' and 'slid_inject' commands
in the `add_llext_target` function by ensuring that the arguments are
expanded correctly before passing them to the shell.

Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
2025-06-06 11:52:31 +02:00
Tom Hughes
b6766aeb6b cmake: compiler: Remove -fshort-enums
"-fshort-enums" changes the ABI. It's not enabled for gcc, so it's not
clear why it's enabled for clang (only ARM) and armclang, other than it
looks like some users of these toolchains may be linking against code
that is compiled with "-fshort-enums".

As an example, when compiling with clang, CONFIG_LTO, and a toolchain
built without "-fshort-enums", the linker warns:

ld.lld: error: linking module flags 'min_enum_size': IDs have
conflicting values in
'/usr/armv7m-cros-eabi/usr/lib/libc++_static.a(string.cpp.o at 784090)'
and 'ld-temp.o'

Signed-off-by: Tom Hughes <tomhughes@chromium.org>
2025-06-06 11:52:22 +02:00
Pieter De Gendt
c773f42013 scripts: list_hardware: Fix linter issues
Fix issues reported by ruff.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2025-06-06 11:52:17 +02:00
Pieter De Gendt
b2687468b5 scripts: list_boards: Fix linter issues
Fix issues reported by ruff.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2025-06-06 11:52:17 +02:00
Dave Joseph
963fda5e4a drivers: mbox: TI Secure Proxy mbox drivers
Added secure proxy mailbox driver for supported devices using
the binding ti,secure-proxy. This is used to communicate with
a device manager running on a separate core via a secure proxy
mailbox for TI K3 devices. Required for enabling TISCI layer
communication.
Refer: https://software-dl.ti.com/tisci/esd/latest/1_intro/TISCI.html

Tested on MAIN_CORTEX_R5_0 on AM243x EVM.
Refer:https://www.ti.com/lit/pdf/spruim2

Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Dave Joseph <d-joseph@ti.com>
2025-06-06 11:52:07 +02:00
Benjamin Cabé
8c6b2c8c88 doc: _extensions: boards: retrieve archs info dynamically
Rather than hardcoding the human readable full names of the archs in the
board catalog, we now retrieve them dynamically from the archs.yml file.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-06-06 10:29:44 +02:00
Benjamin Cabé
a89c79275f scripts: hwm_v2: add full_name property for archs
Allow to specify a human readable full name for archs that can then be
leveraged e.g. in the documentation.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-06-06 10:29:44 +02:00
Benjamin Cabé
061cbb7bc0 scripts: hwmv2: cache pykwalify validators
speed up the various list_*.py scripts by means of caching the
pykwalify core object so that schemas don't get unnecessarily
processed multiple times.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-06-06 10:29:38 +02:00
Henrik Lindblom
24b4ce189f drivers: stm32: dma: fix external dcache support
Several drivers checked for the presense and availability of data cache
through Kconfig symbol. This is supported according to the current
documentation, but the symbol DCACHE masks two types of cache devices: arch
and external caches. The latter is present on some Cortex-M33 chips, like
the STM32U5xx. The external dcache is bypassed when accessing internal
SRAM and only used for external memories.

In commit a2dd232410 ("drivers: adc: stm32: dma support") the rationale
for gating dcache for adc_stm32 behind STM32H7X is only hinted at, but
reason seems to be that it was the only SOC the change was tested on. The
SOC configures DCACHE=y so it is most likely safe to swap the SOC gate for
DCACHE.

The DCACHE ifdefs are now hidden inside the shared stm32_buf_in_nocache()
implementation.

Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
2025-06-06 10:19:58 +02:00
Peter Mitsis
811302e6d2 kernel: sys_heap: Fix chunk size request validation
Updates the heap code to ensure that when converting the requested
number of bytes to chunks, we do not return a value that exceeds
the number of chunks in the heap.

Fixes #90306

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2025-06-06 10:12:19 +02:00
Marcel Krüger
45f3b71b39 input_gpio: Fix not using latest pin state on pm resume
When the device was suspended and the pin level changed during
that time, the pin level of course isn't updated in the pins cb_data.
Once the device is resumed, this leads to potentially having
a wrong value in the pin state data leading to swallowing the first
event due to comparing the stored level vs. the new level before
reporting.

Also added some `const`s and deleted an unused struct element.

Signed-off-by: Marcel Krüger <marcel@mkgr.dev>
2025-06-06 10:12:11 +02:00
Abderrahmane JARMOUNI
b31251b4b4 drivers: stm32: i2c rtio: Fix 'timings' array size
'timings' is an array of 'struct i2c_config_timing' (3 x uint32_t).
'i2c_timings_##index' is an array of uint32_t (hence the cast when it
is assigned to 'timings'). Therefore 'ARRAY_SIZE(i2c_timings_##index)' is
off by a factor 3 when used for n_timings.

Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
2025-06-06 10:11:59 +02:00
Yuval Peress
d17956a074 build: Support SYSROOT_DIR in native_sim and clang
When running naive sim builds using clang, respect user passed
SYSROOT_DIR values. Additionally, allow overriding the archive tool
when calling Make for the native simulator.

Add the sysroot (if available) to the native_simulator target and
TOOLCHAIN_C_FLAGS and TOOLCHAIN_LD_FLAGS. Additionally pass CMAKE_AR
to NSI_AR.

Signed-off-by: Yuval Peress <peress@google.com>
2025-06-06 10:11:49 +02:00
Yishai Jaffe
8a26316f17 boards: st: nucleo_l433rc_p: add die_temp, vref, and vbat nodes
Added die_temp, vref, and vbat nodes and their aliases to the
nucleo_l433rc_p board.

Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
2025-06-06 10:11:42 +02:00
Yishai Jaffe
7fe85f8cb4 drivers: serial: stm32: simplify logic
Simplify the logic for the `uart_stm32_cfg2ll_databits` function
regarding `LL_USART_DATAWIDTH_9B` being defined or not.

Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
2025-06-06 10:11:29 +02:00
Jan Behrens
0f22fde988 boards: shields: Added Mikroe Stepper 18 Click Shield
This shield includes a drv8426 stepper driver and a mcp4726 dac for
current control. Note that the micro-step pins are controlled by
physical switches and are thus not available in Zephyr.

Signed-off-by: Jan Behrens <jan.behrens@navimatix.de>
2025-06-06 10:11:17 +02:00
Jan Behrens
a3d298cb6a boards: shields: Added Mikroe Stepper 19 Click Shield
This shield includes a ti drv8424 stepper driver that is controlled
via gpio. Some of these pins are only available via the tca9538a gpio
expander on the shield.

Signed-off-by: Jan Behrens <jan.behrens@navimatix.de>
2025-06-06 10:11:17 +02:00
Francois Ramu
cbe3e18396 drivers: flash: stm32h7RS flash size is fixed to 64KBytes
Fix the flash size to 64KB for the stm32H7RS series.
Restore the get_size API function for that series.
This is a specificity of this stm32 mcu (RefMan RM0477).

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-06-06 10:11:07 +02:00
Alain Volmat
48a8716dec shields: st_b_cams_imx_mb1854: add stm32n6 specifc confs
Add configuration for the STM32N6 DCMIPP driver which currently
requires to have the sensor pixel format and resolutions set via
KConfig

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-06 10:10:58 +02:00
Alain Volmat
314953b19b dts: arm: st: mp13: add dcmipp node in stm32mp135.dtsi
Add node describing the DCMIPP available on stm32mp135.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-06 10:10:58 +02:00
Alain Volmat
e4f6be0e5d boards: st: stm32n6570_dk: csi_22pins connector related labels
Add csi_22pins_connector and related label in order to use
shields relying on csi_pins_connector.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-06 10:10:58 +02:00
Alain Volmat
9600fc523c boards: st: stm32n6570_dk: Add IC17/IC18 settings for DCMIPP/CSI
Add configuration of the IC17 and IC18 clock dividers, used
by the dcmipp and csi IPs in the stm32n6.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-06 10:10:58 +02:00
Alain Volmat
56e38ee034 dts: arm: st: n6: add dcmipp node
Add node describing the dcmipp in stm32n6.dtsi

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-06 10:10:58 +02:00
Alain Volmat
fea5c421b4 drivers: video: dcmipp: add functions for external ISP functions usage
Add weak functions and their call within the dcmipp driver so that
externally provided ISP control functions can be called by the
driver at right timing in order to perform the control of the
ISP part of the DCMIPP.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-06 10:10:58 +02:00
Alain Volmat
cd8dccf211 drivers: video: introduction of the stm32 DCMIPP driver
The STM32 Digital Camera Memory Interface Pixel Processor (DCMIPP)
is a multi-pipeline camera interface allowing to capture
and process frames from parallel or CSI interfaces depending on its
version.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-06 10:10:58 +02:00
Alain Volmat
a3f9d52d10 dts-bindings: video: addition of stm32 dcmipp description
Addition of description for the STM32
Digital Camera Memory Interface Pixel Processor (DCMIPP).

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
2025-06-06 10:10:58 +02:00
Florijan Plohl
e0bd460de0 drivers: sensor: Add icm40627 6-axis accelerometer driver
Initial driver for the icm40627 from Invensense/TDK, a 6-axis
accelerometer with gyroscope and temperature sensing capabilities.

Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
2025-06-06 10:10:23 +02:00
Noah Pendleton
b377543628 samples: fs: typo in project name
Looked like copy-paste typo from the `samples/subsys/usb/mass` sample.

Signed-off-by: Noah Pendleton <noah.pendleton@gmail.com>
2025-06-06 08:46:04 +02:00
Carles Cufi
03f46db859 include: sys_clock: Fix compilation when SYS_CLOCK_EXISTS is disabled
If `CONFIG_SYS_CLOCK_EXISTS=n`, then
`CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC` will likely not be defined at all.
Fix the compilation by moving the check for it being `== 0` to a
separate preprocessor #if statement.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2025-06-06 08:45:57 +02:00
Tim Lin
97cdedec80 drivers/timer: it51xxx: Compensate time calculation to reduce drift
The EC timer runs at 9.2 MHz, which leads to a non-integer number of
ticks per microsecond. This causes slight overestimation when delays
are computed using whole ticks (e.g., using 10 ticks for 1 µs).
To address this, the busy wait calculation is adjusted with a
compensation factor to minimize cumulative timing error over time.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-06-06 08:45:43 +02:00
Axel Le Bourhis
3c6a3826ad soc: nxp: rw: adjust ACL bt_conn_tx contexts to match Controller's
RW61x's controller uses 8 ACL packets, adjust `BT_BUF_ACL_TX_COUNT`
to match it.

Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
2025-06-06 08:45:33 +02:00
Axel Le Bourhis
df2dac7a68 soc: nxp: mcxw: adjust ACL bt_conn_tx contexts to match Controller's
MCXW7x's controller uses 12 ACL packets, adjust `BT_BUF_ACL_TX_COUNT`
to match it.

Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
2025-06-06 08:45:33 +02:00
Axel Le Bourhis
928aa4a196 drivers: bluetooth: hci_nxp: fix discarding multi part adv reports
In case of extended advertising, advertising data can be reported in
parts, so we shouldn't discard them.
Instead, only discard the legacy advertising reports.

Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
2025-06-06 08:45:33 +02:00
Szymon Czapracki
c91b98c829 tests: Bluetooth: tester: Instructions for btsnoop and RTT logging
Updated the tester README with configuration options required to
build with support for btsnoop and SEGGER RTT log backends. This
helps developers capture logs for debugging and analysis during
Bluetooth testing.

Signed-off-by: Szymon Czapracki <szymon.czapracki@codecoup.pl>
2025-06-06 08:45:23 +02:00
Benjamin Cabé
17ab862169 scripts: ci: add vermin (min python version check)
Add a compliance check that allows to flag when a given file requires a
Python version higher than 3.10 (minimum supported version in Zephyr at
the time of writing) since not all Python scripts are tested against
3.10 in CI and we want to avoid introducing changes that could break
users.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-06-06 08:45:13 +02:00