Introduce TLS socket options, which allow to configure session caching
on a socket.
The cache can be enabled on a socket with TLS_SESSION_CACHE option.
Once cache is enabled on a socket, the session will be stored for re-use
after a sucessfull handshake. If a socket is attempting to connect to a
host for which session is stored, the session will be resumed and mbed
TLS will attempt to use a simplified handshake procedure.
The server-side management of sessions is fully controlled by mbed TLS
after session caching is enabled on a socket.
The other TLS_SESSION_CACHE_PURGE option allows to clear all of the
cache entries, releasing the memory allocated for sessions.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Add Kconfig configuration options which allow to configure
session caching in mbed TLS.
Note, that mbed TLS only takes care of server-side caching, the
application (socket layer) needs to implement a session storage for
client.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
In order to be consistent with what is possible in Devicetree, always
take a period in nanoseconds. Other scales or units may be specified by
using, e.g., the PWM_MSEC() macros (all of them converting down to
nanoseconds). This change then deletes the "_nsec" and "_usec" versions
of the pwm_set call.
Note that this change limits the period to UINT32_MAX nanoseconds,
~4.3s. PWM is, in generali, used with periods below the second so it
should not be a problem.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Simplify the driver by using pwm_dt_spec.
TODO: decide if pwm_dt_spec should also store period.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The sample did not use PWM in a proper way: it relied on a PWM device
handle, but channel or flags were hardcoded in the code. This patch
changes the sample to use a local binding ("pwm-servo") where the `pwms`
property is defined. This allows to make use of pwm_dt_spec facilities,
reducing the overall sample complexity and making it more portable
without editing the source code. The custom binding also requires to
provide the minimum/maximum pulse width so that different servos can be
easily plugged in without the need to edit sources.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Similar to other APIs, this patch introduces the pwm_dt_spec structure
and associated helpers, e.g. PWM_DT_SPEC_GET() or pwm_set_cycles_dt().
The pwm_dt_spec reduces the boilerplate code needed when using
Devicetree. For example, if we have:
led: led {
...
pwms = <&pwm0 1 PWM_POLARITY_NORMAL>;
...
};
One can do now in the application:
struct pwm_dt_spec led = PWM_DT_SPEC_GET(DT_NODELABEL(led));
pwm_set_usec_dt(&led, LED_PERIOD_USEC, LED_PULSE_USEC);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In a first place, the PWM API operates on "channels", not "pins". While
the API calls could have been changed by _channel, this patch takes the
approach of just dropping _pin. The main reason is that all API calls
operate by definition on a channel basis, so it is a bit redundant to
make this part of the name. Because the `_dt` variants of the calls are
going to be introduced soon, the change to `_channels` + `_dt` would
make API function names quite long.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The variable indicating the PWM channel is now names "channel" instead
of "pwm", adjust all drivers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
All PWM API functions take a "pwm" parameter that indicates the selected
PWM channel. The variable name (pwm) and its documentation "PWM pin" is
misleading. This patch changes it to "channel" in line with the
terminology used in Devicetree (see DT_PWMS_CHANNEL... family of
macros).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The timer registers are accessible via the device config field, driver
code was wrong in one case (pwm is the variable indicating PWM channel).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Multiple if/else blocks had missing braces, add them as this violates
Zephyr coding guidelines.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In 92d8329d5b a new DT property was introduced to set the WQ priority
of the instance. The fallback value when the property was not present
was arbitrarily set to <0 PRIO_PREEMPT>.
The problem is that this value is actually changing the behaviour for
the code that is not explicitly setting the DT property, breaking in
some cases the existing code.
Move the default value to <0 PRIO_COOP> to give the old code a
consistent behaviour before and after the 92d8329d5b commit.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Set the top value relative to the current time. This is
so that we avoid the case of setting the top value that
is prior to the current value.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Implement the set_top_value. This reserves one of the Match channels
to set the top value and to reset the counter.
Therefore the number of channels available to the user is reduced by 1.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add a GPIO pass-thru map for accessing the full range (0 to 39) of ESP32
GPIO pins by their datasheet number.
GPIOs 0 to 31 are mapped to gpio0 while GPIOs 32 to 39 are mapped to
gpio1.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit updates the documentation 404 page to suggest filing a
GitHub issue for broken links instead of sending an email or using the
"contact us" form.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
After change in RD into 64-bit time, target time must be express in
absolute 64-bit time. Upper layer e.g. OpenThread still utilizes only
LSB of the RD time therefore the conversion is required.
Make sure that target time is absolute 64-bit target time.
Signed-off-by: Lukasz Maciejonczyk <lukasz.maciejonczyk@nordicsemi.no>
The PWM period was set to 0, a value that is not suitable to drive an
LED using a PWM signal. A period of 20 msec has been chosen, following
other platforms.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
When receiving Transaction Start PDU, assure that number of segments
needed to send a Provisioning PDU with TotalLength size is equal to SegN
value provided in the Transaction Start PDU.
Signed-off-by: Pavel Vasilyev <pavel.vasilyev@nordicsemi.no>
When a memory domain is initialized, the z_libc_partition must be
included so that critical libc-related data can be accessed.
On ARM processors without TPIDRURO when THREAD_LOCAL_STORAGE is enabled,
this includes the TLS base pointer, which is used for several
thread-local variables in the kernel.
Signed-off-by: Keith Packard <keithp@keithp.com>
When active, z_libc_partition consumes an MPU region which leaves too
few for some MPU tests. Free up one by disabling HW stack protection.
Signed-off-by: Keith Packard <keithp@keithp.com>
When using THREAD_LOCAL_STORAGE the thread_userspace_local_data stuff
isn't used, so these tests wouldn't build.
Signed-off-by: Keith Packard <keithp@keithp.com>
The linker_script generating tool needs to ensure that .tdata gets added
to the TLS data section while .tbss is added to the TLS BSS section.
Signed-off-by: Keith Packard <keithp@keithp.com>
Scripts generated with ld_script.cmake also need to have the _align
symbols defined so that they work with TLS values.
Signed-off-by: Keith Packard <keithp@keithp.com>
These two options significantly increase the amount of stack space used
by the logging thread as these generate both additional logging and
generate deep stacks themselves. This fixes running the
tests/subsys/logging/log_core_additional/logging.add.log1 test on
riscv32 with THREAD_LOCAL_STORAGE enabled.
Signed-off-by: Keith Packard <keithp@keithp.com>
The thread switching hooks are invoked in the middle of thread
switching, after the out-going thread registers are saved, but before
the in-coming thread registers are restored, and also before
z_thread_entry is called if the thread is just starting.
When the core is first starting, the TLS base register won't be set at
all, so accessing variables will fault. When switching threads, the
in-coming thread TLS base register will not have been restored, so the
z_tls_current value will end up getting the out-going thread instead.
To fix this, switch from k_current_get() to z_current_get().
Signed-off-by: Keith Packard <keithp@keithp.com>
Set TP in exception context so that it gets loaded into the CPU when
first running the thread. Set TP for secondary cores to related idle TLS
area.
Signed-off-by: Keith Packard <keithp@keithp.com>
When a stack overflow is caught by an MPU region, the stack pointer will
end up inside that area when the exception is handled. Handling the
exception involves pushing an exception frame onto the same stack. If
there's not enough space remaining below the faulting SP value, the
memory region below the stack will get corrupted.
We protect against this by making the stack guard larger than the 0x20
bytes necessary to hold an exception frame. To avoid lots of conditional
complexity here, the guard is set to 0x40 bytes if the MPU minimum size
is not larger than 0x20 bytes.
Signed-off-by: Keith Packard <keithp@keithp.com>
V7-A also supports TPIDRURO, so go ahead and use that for TLS, enabling
thread local storage for the other ARM architectures.
Add __aeabi_read_tp function in case code was compiled to use that.
Signed-off-by: Keith Packard <keithp@keithp.com>
Making context switch cache-coherent in SMP is hard. The
KERNEL_COHERENCE handling was conservatively invalidating the stack
region of a thread that was being switched in. This was because it
might have (1) run on this CPU in the past, but (2) run most recently
on a different CPU. In that case we might have stale data still in
our local dcache!
But this has performance impact in the (very common!) case of a thread
being switched out briefly and then back in (e.g. k_sleep() for a
small duration). It will come back having lost all of its cached
stack context, and will have to fetch all that information back from
shared SRAM!
Treat this by tracking a "last_cpu" for each thread in the arch part
of the thread struct. If we're coming back to the same CPU we left,
we know we can skip the invalidate.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
DAD timeout was wrongly checking the reply order. The code will always
assign sequentially the reply to 0-2 with the current uptime. This means
that we will always have dad[0] < dad[1] < dad[2]. Check it is useless.
Instead, let just check if we got all replies.
The test checking the time between the first and last request is to
fragile. It is testing a constant independently of the tested platform
failing in several of them. Just remove it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add a pair of dt macros for specifying the pwm frequency in hertz or
kilohertz: PWM_HZ and PWM_KHZ. This is then converted in period
nanoseconds so it works as expected with the other definitions.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
