arch/arm: Use TPIDRURO on cortex-a too
V7-A also supports TPIDRURO, so go ahead and use that for TLS, enabling thread local storage for the other ARM architectures. Add __aeabi_read_tp function in case code was compiled to use that. Signed-off-by: Keith Packard <keithp@keithp.com>
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4 changed files with 18 additions and 2 deletions
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@ -33,7 +33,7 @@ config ARM
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# FIXME: current state of the code for all ARM requires this, but
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# is really only necessary for Cortex-M with ARM MPU!
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select GEN_PRIV_STACKS
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select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_AARCH32_CORTEX_R || CPU_CORTEX_M
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select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_AARCH32_CORTEX_R || CPU_CORTEX_M || CPU_AARCH32_CORTEX_A
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help
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ARM architecture
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@ -16,3 +16,4 @@ zephyr_library_sources(
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zephyr_library_sources_ifdef(CONFIG_USERSPACE thread.c)
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zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c)
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zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE __aeabi_read_tp.S)
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15
arch/arm/core/aarch32/cortex_a_r/__aeabi_read_tp.S
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arch/arm/core/aarch32/cortex_a_r/__aeabi_read_tp.S
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@ -0,0 +1,15 @@
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/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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_ASM_FILE_PROLOGUE
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GTEXT(__aeabi_read_tp)
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SECTION_FUNC(text, __aeabi_read_tp)
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mrc 15, 0, r0, c13, c0, 3
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bx lr
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@ -186,7 +186,7 @@ out_fp_endif:
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adds r4, r2, r4
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ldr r0, [r4]
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#if defined(CONFIG_CPU_AARCH32_CORTEX_R)
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#if defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
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/* Store TLS pointer in the "Process ID" register.
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* This register is used as a base pointer to all
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* thread variables with offsets added by toolchain.
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