Commit graph

25 commits

Author SHA1 Message Date
Gerard Marull-Paretas
c925b5991a include: remove unnecessary autoconf.h includes
The autoconf.h header is not required because the definitions present in
the file are exposed using the compiler `-imacros` flag.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-04-05 11:18:20 +02:00
Peng Fan
01002a3c8d nxp: imx: support i.MX8MP EVK board
Support i.MX8MP EVK A53 with/without jailhouse hypervisor
 - Add dts/dtsi
 - Add board file

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-14 11:28:35 +01:00
Peng Fan
9be846bf46 soc: arm64: imx8m: share the dummy file
Move the file from board to soc to make it could be shared by
i.MX8M family. When MCUX_HAL supported in future, this file could
be dropped.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-14 11:28:35 +01:00
Peng Fan
b63c363989 arm64: nxp_imx: drop a53 linker file
We could reuse the common linker script, no need use i.MX8M specific
one. BTW i.MX8M family is based on A53 core.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-14 11:28:35 +01:00
Peng Fan
84081ffddc soc: arm64: nxp_imx: Add i.MX8M Mini SoC A53 support
Add minimal SoC support for the NXP i.MX8M Mini series Cortex-A53 Core.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-03-09 09:56:12 -06:00
Michal Orzel
176240c3c2 xenvm: Add support for using GICv3
Currently xenvm board/soc is configured to use GICv2 and there
is no clean way(without modifying the source code) to alter this
configuration to use GICv3.

Due to the increasing number of users wishing to use GICv3, add
a new configuration called xenvm_gicv3 that enables GICv3.
Create a Kconfig file and add a config XENVM_USE_GIC_V3 that,
if set, will cause SOC_XENVM to select GICv3 instead of GICv2.

Update documentation accordingly.

Take the opportunity to remove the unnecessary config options
from the defconfig files.

Signed-off-by: Michal Orzel <michal.orzel@arm.com>
2022-02-25 22:19:37 -05:00
Gerard Marull-Paretas
300fda03c2 soc: arm64: xenvm: move Kconfig option to soc
The XEN_INITIAL_DOMAIN option was defined at board level, however, some
drivers such as the XEN serial driver has dependencies on
XEN_INITIAL_DOMAIN, meaning any new board has to define its own copy of
XEN_INITIAL_DOMAIN. Move the option to SoC Kconfig.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-02-21 19:35:21 -05:00
Gerard Marull-Paretas
e5e73a70e9 soc: remove unnecessary inclusions of devicetree.h
Many ARM SoCs included <devicetree.h> likely due to:

1. nvic.h not being self-contained
2. As a result of copy-paste

Some RISC-V SoCs had the same problem, in this case likely due to
copy-paste from ARM. The <devicetree.h> header has been removed using
the following command:

sed -i ':a;N;$!ba;s/#include <devicetree\.h>\n//g' soc/**/soc.h

soc.h files that make a legitimate usage of the API have not been
changed.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-01-11 11:52:27 +01:00
Dmytro Firsov
5451674373 xenvm: switch to Xen PV console instead of PL011 SBSA
This commit removes usage of Xen emulated PL011 SBSA UART in favor of
Xen PV console minimal implementation. Now boot log and application
output can be directly taken from hypervisor domain console, instead of
virtual UART.

Also Xen VM doc was updated according to these changes.

Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
2021-10-29 15:23:33 +02:00
Siew Chin Lim
ccebf5885f soc: arm64: Add Kconfig files for Intel SoC FPGA
Add Kconfig files for intel_socfpga folder.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-10-12 08:37:03 -04:00
Siew Chin Lim
f1a6cc14c0 soc: arm64: Add MMU table for Intel SoC FPGA Agilex
Add MMU table for Intel SoC FPGA Agilex initial bring up.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-10-12 08:37:03 -04:00
Siew Chin Lim
31f5f511eb soc: arm64: Add common header files for Intel SoC FPGA
Add common header files for Intel SoC FPGA. The header files define the
handoff data structure and system manager base addresses needed by
Agilex initial bring up.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-10-12 08:37:03 -04:00
Jaxson Han
fa494e78b2 soc: arm64: Adjust the fvp_aemv8r's data region
When userspace enabled, the zephyr data region should start from
_app_smem_start instead of __kernel_ram_start.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2021-09-28 20:06:06 -04:00
Jaxson Han
34d6c7caa7 arm64: cortex_r: Move mpu code to a better place
This patch mainly moves mpu related code from
arch/arm64/core/cortex_r/mpu/ to arch/arm64/core/cortex_r/ and moves
the mpu header files from include/arch/arm64/cortex_r/mpu/ to
include/arch/arm64/cortex_r/

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2021-09-28 20:06:06 -04:00
Neil Armstrong
f5ac88f166 soc: fvp_aemv8a: enable 16384 IRQs to permit using up to 8192 LPIs
When using ITS, the LPI range starts at 8192 and by default support
8192 LPIs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-09-28 19:45:29 -04:00
Torsten Rasmussen
3d82c7c828 linker: align _image_text_start/end/size linker symbols name
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.

The symbols _image_text_start and _image_text_end sometimes includes
linker/kobject-text.ld. This mean there must be both the regular
__text_start and __text_end symbols for the pure text section, as well
as <group>_start and <group>_end symbols.

The symbols describing the text region which covers more than just the
text section itself will thus be changed to:
_image_text_start -> __text_region_start
_image_text_end   -> __text_region_end

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Torsten Rasmussen
c6aded2dcb linker: align _image_rodata and _image_rom start/end/size linker symbols
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.

The symbols _image_rom_start and _image_rom_end corresponds to the group
ROMABLE_REGION defined in the ld linker scripts.

The symbols _image_rodata_start and _image_rodata_end is not placed as
independent group but covers common-rom.ld, thread-local-storage.ld,
kobject-rom.ld and snippets-rodata.ld.

This commit align those names and prepares for generation of groups in
linker scripts.

The symbols describing the ROMABLE_REGION will be renamed to:
_image_rom_start -> __rom_region_start
_image_rom_end   -> __rom_region_end

The rodata will also use the group symbol notation as:
_image_rodata_start -> __rodata_region_start
_image_rodata_end   -> __rodata_region_end

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Huifeng Zhang
a1f14419ee soc: arm64: arm: fvp_base_r: define a strong pm_cpu_on() function
With this patch, zephyr can enable SMP directly. Otherwise
zephyr needs TB-R to provide psci function.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2021-07-13 09:30:29 -04:00
Huifeng Zhang
b89c727c8e soc: arm64: arm: fvp_aemv8r: Init VMPIDR_EL2 in el2 plat init.
Add strong definition z_arm64_el2_plat_init() and it is controlled
by CONFIG_SOC_FVP_AEMV8R_EL2_INIT.

VMPIDR_EL2 must be set manually on EL2. The purpose of VMPIDR_EL2 is
that holds the value of the Virtualization Multiprocessor ID and This
is the value returned by EL1 reads of MPIDR_EL1

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2021-07-13 09:30:29 -04:00
Carlo Caione
0427d93f4a board: arm64: Add FVP Base RevC 2xAEMv8A board
Add support for the FVP Base RevC 2xAEMv8A board to be emulated using
the same FVP. For now the virtual platform is only exposing one core and
the basic set of peripherals (GICv3, ARM arch timer, PL011, etc...).

INFO    - Total complete:  256/ 256  100%  skipped:  933, failed:    0

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-04-27 13:30:07 -04:00
Jaxson Han
f249544f48 arch: arm64: Add MPU drivers to the build system
When ARM_MPU is defined, the MPU drivers will be built into the final
zephyr target.

Signed-off-by: Haibo Xu <haibo.xu@arm.com>
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2021-04-13 07:47:44 -04:00
Jaxson Han
318a1a1d38 soc: arm64: Define Armv8-R aarch64 default MPU regions
Add several default mpu regions(flash/sram/sram_text/sram_ro) for
the Armv8-R aarch64 based Soc.
These regions will be initialized as static region during system boot.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2021-04-13 07:47:44 -04:00
Jaxson Han
ade060ed1f soc: arm64: Add FVP AEMv8R AArch64 soc
Add essential files to create a new soc.
Introduce a new type of soc series named fvp_aemv8r.
Add a new soc named fvp_aemv8r_aarch64.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2021-04-13 07:47:44 -04:00
Jiafei Pan
34378d611b soc: arm64: add NXP ls1046a support
NXP ls1046a is SoC includes the following functions and features:
1. Four 32/64-bit Arm v8 A72 CPUs
2. Cache coherent interconnect (CCI-400)
3. One 32/64-bit DDR4 SDRAM memory controller with ECC
4. Peripheral interfaces include DPAA network, PCIe, USB, SPI,
   GPIO, UART, SDHC, IFC, LPUART ...

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2021-04-09 13:25:15 +02:00
Carlo Caione
3539c2fbb3 arm/arm64: Make ARM64 a standalone architecture
Split ARM and ARM64 architectures.

Details:

- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
  (arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
  boards/bcm_vk/viper directory

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-31 10:34:33 -05:00