Back with commit a1b77fd589 huge chunk of code was automatically
refactored using a script, which in turn left some macros meaningless
Signed-off-by: Hristo Mitrev <hr.mitrev@gmail.com>
Just use dev->name. This change follow same principles applied when
DEV_CFG and DEV_DATA macros were removed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Move the can_set_bitrate() function to can_common.c as it is getting
quite long for a static inline function.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for getting the maximum supported bitrate in bits/s for CAN
controller/transceiver combination and check that a requested bitrate is
within the supported range.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for the new pinctrl API to the nRF PWM driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF QDEC driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF QSPI NOR flash driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for configuring pins to be used by the nRF PWM, QDEC, and
QSPI peripherals.
A new custom property "nordic,invert" is added to the pin configuration
group binding to allow configuring PWM channel outputs as inverted.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the DMIC driver that handles
the nRF PDM peripheral. Update code of the driver and the related
devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add support for the new pinctrl API to the nRF I2S driver. Update code
of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
I introduced some errors during the gpio_dt_spec/i2c_dt_spec conversion
process. This patch fixes the issues so that driver builds.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Driver implementation for the Xilinx Processor System MIO / EMIO GPIO
controller as contained in the Zynq-7000 and ZynqMP (UltraScale) SoCs.
The driver is split up into source and header for a parent controller
device and source and header for 1..n child GPIO pin bank devices.
The parent device driver takes care of IRQ handling, the GPIO pin bank
driver provides pin / bank access according to the API defined by the
GPIO subsystem.
More than one device for this type of GPIO controller is required as
it provides access to a number of GPIO pins well in excess of the 32
pins addressable by the current GPIO API (whereever parameters or
return values come in the form of a bit mask):
- Zynq-7000: 54 MIO GPIO pins, 64 EMIO GPIO pins in 4 banks.
- ZynqMP: 78 MIO GPIO pins, 96 EMIO GPIO pins in 6 banks.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Use the devicetree properties to determine if the dedicated temperature or
voltage reference channels should be configured for the ADC.
Fixes#43750.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
The stm32's I2C peripheral has a maximum transmission size. Larger trans-
action, that I2C itself allows, can be achieved be using the peripheral's
reload-mode.
In order to do that, st's low-lever drivers need to be informed according-
ly. The previous iteration of the code mishandled the next_msg_flags para-
meter, causing the issue to manifest itself.
This refactors the inner loop of i2c_stm32_transfer() into its own func-
tion. This passes the message parameter by value in order to be able to
mutate its state while keeping the original datum from the user intact
during the entire procedure.
Fixes#43235
Signed-off-by: Frank Terbeck <ft@bewatermyfriend.org>
Claim the net_context mutext associated with a socket before claiming
the socket mutex. The receive callback claims the net_context mutex
internally, which will now always succeed immediately.
The TX path claims the net_context mutex before the socket mutex, and if
we don't use the same order, we can end up in a deadlock.
Fixes#43470.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
It may happen that after the flash chip was previously put into
the Deep Power Down mode, the system was reset but the flash chip
was not. Consequently, the flash chip can be in the DPD mode when
the QSPI driver is initialized. Some flash chips will just exit
the DPD mode on the first CS pulse, but some need to receive the
dedicated command to do it and they will not respond to any other
commands including those that the driver need to perform to complete
its initialization ("Read status register" and "Read JEDEC ID").
This commit adds sending of the "Release from Deep Power Down"
command right after initialization of the QSPI interface to avoid
the problem described above.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Previous commit 579ca90e25 to
build wifi drivers as a library changed the include path for
the WINC1500 driver, which results in the include path being
local to the library. However, the Atmel HAL requires
wifi_winc1500_nm_bsp_internal.h to in the search path. So
change the include path to be global.
Fixes#43456
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Refactors the remaining I2S drivers to use the shared driver class
initialization priority configuration, CONFIG_I2S_INIT_PRIORITY, to
allow configuring I2S drivers separately from other devices. This is
similar to other driver classes.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to be
consistent with other driver classes.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Fix register bit field when clock source is MSI
on the stm32L0x or stm32L1x mcus
Use RCC_CR_MSIRGSEL bit field instead of not soc stm32wbx serie
That bit of the RCC CR is common to several stm32 mcus
Signed-off-by: Francois Ramu <francois.ramu@st.com>
After experiencing a few deadlocks, it was discovered that this bus does
not implement any form of mutual exclusion... this patch addresses this
and resolves potential deadlocks.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Refactors interrupt controller drivers to use the shared driver class
initialization priority configuration, CONFIG_INTC_INIT_PRIORITY, to
allow configuring interrupt controller drivers separately from other
devices. This is similar to other driver classes.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEFAULT to preserve
the existing default initialization priority for most drivers.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Refactors the remaining I2C drivers to use the shared driver class
initialization priority configuration, CONFIG_I2C_INIT_PRIORITY, to
allow configuring I2C drivers separately from other devices. This is
similar to other driver classes.
The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the
existing default initialization priority for most drivers.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Enable second usb EHCI if usb2 node has status="okay" Note that this
driver is still an single instance driver, this change simply enables
the driver to work with the usb2 peripheral if that one is enabled, and
usb1 is disabled.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This change includes special handling of the internal voltage
reference and internal die temperature channels for all currently
defined STM32 models
The code now looks for specific ADC + channel ID pairs instead
of just a channel ID to determine if the caller is trying to
configure an internal channel.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
Only call the state change callback if the state has changed. Reuse the
existing function for retrieving the CAN controller state instead of
having the same code twice.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The temperature sensor used in the clock_control driver requires
multithreading, but this is not compatible with mcuboot builds with
multithreading disabled.
Fixes#41597.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
bmi160.c module defines DT_DRV_COMPAT, but bmi160_trigger.c doesn't.
This causes a catastrophic chain of events.
The bmi160.c module includes bmi160.h,
in which the macro DT_ANY_INST_ON_BUS_STATUS_OKAY
affects the size of bmi160_bus union.
So bmi160.c defines a bmi160_cfg struct which contains that union.
Now, in bmi160_trigger_init we get a pointer to that config struct.
The fact that this module now includes bmi160.h without
DT_DRV_COMPAT, causes it to think the union is empty.
That doesn't cause compilation error, just undefined behaviour,
In which you address an empty struct fields.
In general, I suggest that someone makes sure it doesn't happen
in other drivers as well. The problem presented here is general,
meaning that if an h file assumes someone defined DT_DRV_COMPAT
before and it doesn't,
it may lead to some weird behaviour, like the one described.
Signed-off-by: Avi Green <avigreen1978@yandex.com>
gpio_pin_interrupt_configure asserts that one of GPIO_INT_ENABLE or
_DISABLE is specified by the caller, and also that GPIO_INT_EDGE is
requested if both states (GPIO_INT_TRIG_BOTH) should interrupt. This
change corrects the misuses in it8xxx2 drivers that cause assertion
failures.
When assertions are disabled the existing code works correctly because
the it8xxx2 GPIO driver assumes that a pin interrupt should be enabled
if _DISABLE is not requested, and the driver only supports edge
triggers but assumes the absence of GPIO_INT_MODE_LEVEL indicates
an edge trigger was requested.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I1aaee190ec4cf063f36e25c0c293a91d280e71bb
On 32bit compiler the BIT_MASK(32) generate a warning,
after discussion on #42226 and #42163, advise was to use
BIT64_MASK instead.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
These definitions are required to be able to use GICv3
interrupts controller on an ARMv8 AArch32 processor.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
When using DMA to transfer over the spi, the spi_stm32_cs_control
is done after enabling the SPI. The same sequence applies
in the transceive_dma function as in transceive function
Signed-off-by: Francois Ramu <francois.ramu@st.com>
I2C clock and I2C gpio could be on same gpio group.
Remove assertion that required them to be on different
group.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
