The MCP9808 supports threshold triggering. Add support for this feature
in the driver and the sample application.
If triggering is activated, the driver can create its own fiber or use
the system-wide sensor fiber.
Origin: Original
Change-Id: Ie825a22245cb48cbdffba3049011e4d305975d53
Signed-off-by: Vlad Dogaru <vlad.dogaru@intel.com>
The driver only supports simple temperature readings. It does not
support the alarm feature. Datasheet available at
<http://ww1.microchip.com/downloads/en/DeviceDoc/25095A.pdf>.
Origin: Original
Change-Id: I283e6697fc6947975323d280f5ff0ba625fac5a9
Signed-off-by: Vlad Dogaru <vlad.dogaru@intel.com>
Making pinmux depend on GPIO breaks many tests and configurations
when running on real hardware. This should be added as local
configuration in the defconfig instead.
Change-Id: Ibbf1c9a3428ed692937383bf85218b0c120cbe44
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
According to documentation, there must be at least one cycle delay
between two consecutive writes of the DR register. Apparently, this is
true for reading too, though undocumented.
The read_dr() inline function is called as follows:
*(spi->rx_buf) = read_dr(info->regs);
which the compiler, with full optimizations on, turns it into:
ld_s r2,[r1,24] <- the spi->rx_buf
sr 0x80000000,[r4] <- this is the strobe bit write !!!
lr r4,[r4] <- this is the FIFO read!!!
stb r4,[r2] <- store the result
Unfortunately, the read from the FIFO is always 0 since the FIFO data is
not yet available.
During my investigations, I found that the following code works:
sys_out32(1 << 31, info->regs + 0xd);
*(spi->rx_buf) = sys_in32(info->regs + 0xd);
This does, basically, the same thing. But the compiler inserts an
instruction in between the write/read:
sr 0x80000000,[r4] <- write of the strobe bit!!!
ld_s r2,[r1,24] <- the pointer goes to r2
lr r4,[r4] <- read from FIFO!!!
stb r4,[r2] <- store the result
A single clock cycle between writing the register and reading seems
to be enough for the data to become available for reading.
This patch adds a nop in the read_dr() inline function.
Change-Id: I0c216d5738d5771835b1052e2e83363e8e3abf0c
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@intel.com>
This creates the QMSI comparator driver which is simply a shim driver
based on the comparator driver provided by QMSI BSP.
In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_AIO_COMPARATOR=y
CONFIG_AIO_QMSI_COMPARATOR=y
Origin of the file: Original
Change-Id: Iad01cb80f7bb1eff1710cd76cd0afeb70c311e04
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This patch extends the UART QMSI driver so it supports the IRQ APIs from
include/uart.h. The IRQ APIs are enabled by the 'CONFIG_UART_INTERRUPT_
DRIVEN' option.
Differently from others APIs such as I2C and SPI, the UART API is very
low level. For that reason, the IRQ facilities (e.g. irq based transfers)
from the QMSI driver are not useful to the shim driver at the moment. In
order to implement the IRQ APIs we rely on UART registers defined by QMSI.
QMSI UART header is missing some macro definitions from IRR register so
we define them in the shim driver.
Since the IRQ trigger condition is not configurable in the QMSI shim
driver, this patch also changes drivers/serial/Kconfig so the "UART
IRQ Trigger Condition" choice doesn't appear on the menu if the QMSI
driver is selected.
Change-Id: Idf9a0f6a47af2a550a31f474d721068dca989713
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch extends the UART QMSI driver so it supports line control and
driver command APIs.
The line control function supports the baud rate option only (LINE_CTRL_
BAUD_RATE) and, at the moment, the QMSI driver doesn't have any custom
command.
Change-Id: Icc10cb39b4077ed4ccfefb1f0feecec75b79d67c
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch extends the UART QMSI driver so it supports different baud
rate configurations. The baud rate is set per UART controller via
menuconfig. The default baud rate is 115200.
Change-Id: Iad736d72bd309b8a33ab5d538251fce374e89fd2
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch introduces the QMSI UART driver which is simply a shim driver
based on UART driver provided by QMSI BSP.
This initial version implements only the mandatory APIs 'poll_in',
'poll_out' and 'err_check' which are required by trivial sample apps and
by output functionality from the console driver. The remaining APIs will
be implemented by up coming patches. The driver supports only 115200 baud
rate at the moment.
In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_SERIAL=y
CONFIG_UART_QMSI=y
This driver has been tested with Quark SE Devboard so this patch also
adds its platform-specific default configuration options to 'arch/x86/
soc/quark_se/Kconfig'.
Change-Id: Ibde1825d4b0349a376a8e7d91cc9de306946b62f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This reverts commit 0d50329105.
This breaks sanitychecks in CI. The early_sleep kernel test case is failing
randomly.
Change-Id: I015f20699c052b4089076699fc0180945c4d3d16
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The driver should read the mac address from the chip but in
case of cc2520, the chip does not have it. So generate a
random mac address for this invocation of the device.
Change-Id: I2d0cf2ee70525e7f5e65da9fb8ceaa1a2dccecdd
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Now that the internal libc has the off_t type it's the natural choice
for the offset parameters in the flash API.
Change-Id: I69999999625b46634f6d3008fe1b3f82c17d357c
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
This makes the ordering consistent e.g. with SPI, Bluetooth and
Networking APIs. This also follows the order of parameters in the
POSIX read/write APIs.
Change-Id: I4f11c8c90ccadf176d79f6a7bbd98aac61c26cf5
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
size_t is the natural type for any integer that describes a number of
bytes. For the actual data use void pointers to avoid callers having
to do explicit typecasts if the data doesn't originate in a uint8_t
array. Also use a const pointer for writing to avoid typecasts for
data that originates in a const location.
Change-Id: Idbfc14b2d61ca6189411b211c3727f857dbd4059
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Fix dependencies of K64 PWM config options so that they do not appear at
incorrect places in the menuconfig tree hierarchy.
Change-Id: Iea8077400a1bdf3ef1c38b3bf45b7a72373bd096
Signed-off-by: Maciek Borzecki <maciek.borzecki@gmail.com>
Add support for task_sleep() and fiber_sleep() during the
system initialization. When CONFIG_NANO_TIMEOUTS defined,
before the k_server() starts, kernel uses nanokernel
system clock announce and task sleep functionality.
To give device drivers early sleep functionality, the system
clock has to start on SECONDARY initialization level, same
as most of the drivers.
Change-Id: I5b3cf3da4c8d8398a966e901ab211f2fcee18dd6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Implement GATT write without response, no signing yet.
Change-Id: Id676202ab270cf3f0b06ede26dee2f84a9965e09
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Config options 'Clock Radio and 'Serial Delay' appeared out of ADC menu
due to a missing dependency on ADC_QMSI.
Change-Id: Ia1ca0d5a4ea676205a5928689c2adee9e26c2691
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Support for Freescale/NXP K64 SPI modules, limited to:
- Master mode
- A single active set of clock and transfer attributes (CTAR0), which
includes non-adjustable delay parameters
- Tx FIFO fill and Rx FIFO drain interrupt handling
- Standard, continuous select and continuous SCK SPI transfer formats
Also, divide-by-zero code generation in this driver is prevented.
The 'volatile' attribute is added to some of the variables in the baud
rate and delay calculation functions of the K64 SPI driver in order to
prevent bad code generation by gcc toolchains for ARM seen when an
optimization setting above -O0 is used.
Specifically, a register is loaded with the constant 0 and is used as
the divisor in a following divide instruction, resulting in a
divide-by-zero exception.
This issue has been seen with gcc versions 4.8.1 (the VxWorks toolchain)
and 5.2.0 (the Zephyr SDK toolchain).
Change-Id: Ib5b2b748aad8fdfd5e8d40544e6e1abef3713abe
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
PWM support using the Freescale K64 FlexTimer Module (FTM)
Change-Id: Iaad429c01bd877babba04e84d6a4679bd7e38120
Work-by: Mike Hirst <michael.hirst@windriver.com>
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
Interrupt and callback function support is added to the K64F GPIO driver.
The implementation is based on the Designware GPIO driver (gpio-dw.*).
Change-Id: Id88d06f748400f8f822ca98e098cb44a53678c38
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
K64 pinmux support is created as a normal driver.
As opposed to the Galileo board, the pin configuration options are
defined by the MCU and are not board-specific. Separate
platform/board-specific configuration code uses the pinmux driver for
the default pin settings. For FRDM-K64F, only the Arduino pins (22 of a
possible 160) are set up.
Some of the I/O pins routed to the Arduino header are also configured as
JTAG/SWD signals by default and are used by the OpenSDAv2 debug
interface. Therefore, a PRESERVE_JTAG_IO_PINS config option was created
for the FRDM-K64 platform to prevent the default pin settings from
re-configuring these pins.
The K64 MCU separates pin configuration and control, implemented in the
pinmux driver, from GPIO. This results in some cross referencing
between the K64 GPIO driver and the K64 pinmux driver due to the
dependencies of one on the other.
This pinmux driver also uses the expanded pinmux function/mode parameter
size to describe pin configuration options with bit fields for the K64,
including up to 8 pin functions, plus interrupt, pullup/down, drive
strength, open-drain and slew rate.
The following GCC warnings in the K64 pinmux driver are prevented when not
compiling with 'no-optimization' (-O0):
warning: 'gpio_dev' may be used uninitialized in this function
[-Wmaybe-uninitialized]
Change-Id: Ie5031d18750143bf895883058b3cd55fd9989fd3
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
Implement GATT read reusing gatt_private to store GATT parameters.
Change-Id: Ie3c58a6272cc7cf380e4d3a04e45b191680d1ebe
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
The pinmux API was modified to expand the meaning of the 'func' argument
to allow it to represent more than a pre-configured function. This was done
to reasonably accommodate a larger range of pin configuration options
offered by other MCUs, such as the Freescale K64 (up to 8 pin functions,
plus interrupt, pullup/down, drive strength, open-drain, slew rate, etc.).
This allows bit fields to be used to define various settings.
Change-Id: I2b216b822c6bae7133eed01c8c3339bb47b6c5db
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
Basic driver support for the Freescale K64 GPIO module.
Note that only pin direction, read and write are supported.
Change-Id: I6587bb260197a00497be9ac991002e3dde54718d
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
Fix dependencies for external and sensor clock device names in
clock_control Kconfig.
Change-Id: I708f025cf3ce97bcd003754fb5b395712d203107
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
bt_auth_cancel can be used to cancel any type of pairing.
Change-Id: Ia1a6ba834186ab6d5082d3eb473319c2d70cf4a7
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
Rearrange headers so that internal header files gap_internal.h and
gatt_internal.h do not source headers, they are included in *.c files.
Change-Id: I6450ab90eec1b450ee8a138da2ed72b8aaeaf616
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Update RPC functions and data types, works with NBLE firmware
niko-0301
Change-Id: I3538fab1d20c6e140d995a797d68486be6cd0f23
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
This patch fixes the RTC_DW configuration option. DesignWare and QMSI
drivers shouldn't have any dependency from each other. All driveris
are following this policy, but the RTC.
Change-Id: Ic6bdef492d26978aa875c54d41ef39d407ddf4e1
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
SPI flash sub-driver to support WinBond SPI flash.
It is based on the generic flash driver framework.
Change-Id: I58202e38445a052fa0556b03f854e75ef836e2dd
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
This uses ATT Indicate Value command to indicate changes and wait for
confirmation response.
Change-Id: I123a00e374929d779f96a02440215c32c0e79423
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
The arguments to memset in pci_header_get were passed in the wrong
order, causing the memset to be a no-op. Fix this.
Change-Id: I1ea6d7d87d74cff6fec9bbc88c99a4b0e460cc95
Signed-off-by: Shaul Triebitz <shaul.triebitz@intel.com>
Signed-off-by: Ido Yariv <ido@wizery.com>
Implement GATT nble_gattc_disc_rsp() function, may be tested with
bluetooth shell app.
Change-Id: I80c9596e83310902de40f6e91d2ecd4b5d2f3292
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
This creates the QMSI ADC driver which is simply a shim driver based
on the ADC driver provided by QMSI BSP.
In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_ADC=y
CONFIG_ADC_QMSI=y
Optionally this can be set:
CONFIG_ADC_IRQ
CONFIG_ADC_PRI
CONFIG_ADC_QMSI_POLL
CONFIG_ADC_QMSI_INTERRUPT
CONFIG_ADC_QMSI_CALIBRATION
CONFIG_ADC_QMSI_CLOCK_RATIO
CONFIG_ADC_QMSI_SERIAL_DELAY
CONFIG_ADC_QMSI_SAMPLE_WIDTH
Origin of the file: This file has been created from scratch
Change-Id: Ie04776ac2ed88e56852409070edec568974f8e0d
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
This creates the QMSI PWM driver which is simply a shim driver based
on the PWM driver provided by QMSI BSP.
In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_PWM=y
CONFIG_PWM_QMSI=y
Optionally this can be set:
CONFIG_PWM_QMSI_NUM_PORTS=Number of ports available, default is 1
Origin of the file: This file has been created from scratch
Change-Id: Icac90154d020babca1c11147056a3438b84b0d3f
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
The peripherals utilizing UART were required to register their own
ISR rountines. This means that all those peripherals drivers need
to know which IRQ line is attached to a UART controller, and all
the other config values required to register a ISR. This causes
scalibility issue as every board and peripherals have to define
those values.
Another reason for this patch is to support virtual serial ports.
Virtual serial ports do not have physical interrupt lines to
attach, and thus would not work.
This patch adds a simple callback mechanism, which calls a function
when UART interrupts are triggered. The low level plumbing still needs
to be done by the peripheral drivers, as these drivers may need to
access low level capability of UART to function correctly. This simply
moves the interrupt setup into the UART drivers themselves. By doing
this, the peripheral drivers do not need to know all the config values
to properly setup the interrupts and attaching the ISR. One drawback
is that this adds to the interrupt latency.
Note that this patch breaks backward compatibility in terms of
setting up interrupt for UART controller. How to use UART is still
the same.
This also addresses the following issues:
() UART driver for Atmel SAM3 currently does not support interrupts.
So remove the code from vector table. This will be updated when
there is interrupt support for the driver.
() Corrected some config options for Stellaris UART driver.
This was tested with samples/shell on Arduino 101, and on QEMU
(Cortex-M3 and x86).
Origin: original code
Change-Id: Ib4593d8ccd711f4e97d388c7293205d213be1aec
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Not all of the variables defined in the driver data structure are
required. So put some #ifdef around them.
Change-Id: I08a0c02d9e5c6885d9b4d6237446bdb9b98f3bfa
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The I2C has minimum timing requirements for clock signal.
This patch adds the code to make sure the minimum timing
requirements are met.
Change-Id: I3f148433e60be73866577fbe614b892481d7f69d
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Fixed an issue where STOP would be sent twice when a read message
is only 1 byte.
() Skip resetting the controller when NACK is received. This is not
an issue with the controller, so there is no need to reset
the controller and its state machine.
() Cosmetic changes to trim lines > 80 characters.
Change-Id: If2c3b2728b3f088f7aa1fcaa6d2303ff5c4c197d
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There's no reason to require callers to cast their data to uint8_t *
when the data might e.g. originate in a packed struct or some other
data type. Instead, be nice to callers and let them use any pointer
they want. Additionally, declare the TX buffer as a const pointer so
unnecessary typecasts aren't needed for that either (if the data
originates in a const location).
Change-Id: I1482ca4e350b5a7fbda6871ed9f54f255af3aa9e
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
This log is in spi_intel_configure, not in spi_intel_transceive.
Change-Id: I5d62dd63d0cfa2c86f2dd5f9a6d367b7ad47b355
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The buffers aren't guaranteed to be aligned so that they're always
aligned for uint16_t or uint32_t data. Use the available unaligned
access macros to read/write the data.
Change-Id: Ie87c108aa370af196b9c759b59ed7fb9d1ed6183
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Make this explicit to conform to the abstraction layer
defined in include/irq.h
This only worked before because the preprocessor was
substituting the function prototypes.
Change-Id: Id4d46b01f1c53c3a942772640023e23796eeb43b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
When configured at a frequency of 2MHz, a transaction writing
3 bytes and reading 1 byte fails silently (last byte cannot be
read back from the device). Enabling CONFIG_SPI_DEBUG fixes the
issue.
Scope traces show that the transaction (from /CS assert to /CS
deassert) takes 14us and there is activity on the MOSI line
after /CS is deasserted. A transaction writing 2 bytes and reading
3 bytes take 22us.
The issue is due to the fact that completed() deasserts /CS after
the driver has put 3 bytes in the TXFIFO and taken 1 byte from RXFIFO.
Just because the last byte made it to the TXFIFO, it doesn't mean that
it was put on the MOSI line.
The fix:
For a transaction sending T bytes and expecting R bytes, let N=max(T,R).
Send exactly N bytes and wait for exactly N bytes (or an error). This
way, we are sure that all the bytes were sent to the target device.
Also:
Stop calling pull_data() after every byte sent, it might take a while
for a byte to show up in RXFIFO.
If RFS bit is set, stop sending bytes (will be really useful with a
bigger RFT).
Flushing RXFIFO in spi_intel_transceive() is not needed anymore.
Change-Id: Ifb06a12b03e3e20d6ace4d9f3a20fc11ec3bb010
Signed-off-by: Vlad Lungu <vlad.lungu@windriver.com>
