During devicetree macro changes, LPSRAM_BOOT_VECTOR_ADDR
pointed to another macro which was renamed to a non-existent
one. Fix it so that SMP builds again.
Fixes#24720
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Rename DT_L2_SRAM_* to just L2_SRAM_* and set it using new DT macros.
Do something similar for DT_LP_SRAM_* renamed to LP_SRAM_*
Updated the intel_gna driver as it used the DT_L2_SRAM_* defines.
This change also lets us remove dts_fixup.h on intel_s1000 and
intel_apl_adsp SoCs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Due to fake IDT_BASE address, zephyr_prebuilt.elf is about 1.1GB
in size due to all the empty space between end of SRAM and IDT_BASE.
So move the IDT_BASE to the empty space just after SRAM. The section
will be discarded in the final zephyr.elf so it should not be a big
issue. After this change, zephyr_prebuilt.elf is now a bit smaller
than 5MB.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The starting 192kB SRAM is reserved for the mcubootloader. Exclude
this region while building an application to be loaded by mcubootloader.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
All text, data and bss sections are all mapped to the same physical
memory (SRAM). This patch removes the individual section limits
and defines a common limit for the sum of text, data and bss sections.
This would make it more flexible for application developers.
Fixes#11268.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
These changes were obtained by running a script created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:
1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
#define X Y)
3. Check if that name is also the name of a Kconfig option
3.a If it is, then do nothing
3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
(.c, .h, .ld)
Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.
Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-09-13 00:56:48 -04:00
Renamed from arch/xtensa/soc/intel_s1000/memory.h (Browse further)
