Following updates previously done for other drivers, rename all
occurrences of S32 to NXP S32 to avoid ambiguity.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This fixes deadlock that happened waiting for meta data in system
workqueue.
The meta data always get freed in the system workqueue,
so if we're in the same workqueue but there are no immediate
contexts available, there's no chance we'll get one by waiting.
Fixes: #53455
Signed-off-by: Mariusz Skamra <mariusz.skamra@codecoup.pl>
Add support FD frame filter to configure type frame for
each Rx msg to receive corresponding frames (classic, FD frames).
The Bosch M_CAN driver does not support FD frame filter,
so inmplement driver to handle it in software.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
When scanning for available elfs, twister discards ones with `_pre`
in their name, to not include prebuilds like 'zephyr_pre0.elf`.
However, the scan looks at the whole test name. If _pre is in the name
(e.g. _precision) it would be wrongly discarded ending with twister
reporting error that no elfs were found. This commit makes the discard
to look only at the last part of the name (i.e. not including test name
but only a lowest level, where zephyr.elf etc are located.)
Signed-off-by: Maciej Perkowski <Maciej.Perkowski@nordicsemi.no>
The number of extended filters can be up to 15 for MCUs like the NXP
LPC55Sxx series, so the flags don't fit into uint8_t.
Fixes#53417
Signed-off-by: Martin Jäger <martin@libre.solar>
hal_espressif systimer HAL calls are based on 1MHz reference.
This changes systimer driver to allow max clocking reference of 16MHz
and increases soc tick resolution by reducing min delay interval.
This also sets all ESP32-C3 socs to 16MHz hardware cycles reference.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The LCG method used earlier in the random number generator was problematic,
as the lowest bits repeated periodically (for example, the generated number
always resulted in an odd-even-odd-even-.. sequence, or the last three bits
formed an cycle of the length 8). This is because the LCG was done module
2^32. Any LCG using a power of 2 as the modulus will cause the same issue.
The used RNG method was changed to Marsaglia's xor shift-algorithm,
which does not have this issue.
Signed-off-by: Artur Hadasz <artur.hadasz@nordicsemi.no>
ISO/IEC 9899:1999 (C Standard), §7.4 Character handling <ctype.h>:
In all cases the argument is an int, the value of which shall be
representable as an unsigned char or shall equal the value of the macro
EOF. If the argument has any other value, the behavior is undefined.
So add a cast to unsigned char to make sure we do not trigger UB.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Signed-off-by: Felipe Neves <felipe.neves@linaro.org>
west: format manifest to the correct notation.
Co-authored-by: Kevin Townsend <kevin@ktownsend.com>
Add sample to test memory controllers that map external RAM into
SOC address space. This sample uses the "sram-ext" alias
node to determine the base address and size of the external RAM
device.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable APS64 PSRAM on FlexSPI2 bus, running at 200MHz. This PSRAM is
accessible via the memory mapped AHB region for FlexSPI2 when
CONFIG_MEMC=y
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add missing interrupts property for second FlexSPI device on RT5xx.
This interrupt is shared between both FlexSPI devices, but the memc
driver does not use interrupts so no conflict should arise.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for configuring FlexSPI1 clock speed to RT5xx soc
initialization, so that memory present on FlexSPI1 can be accessed.
Note that FlexSPI1 is referred to as FlexSPI2 in the dts files for this
SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce driver for APS6408L PSRAM, built on top of the MCUX memc
driver for flexSPI. This driver supports operating the PSRAM in high
speed mode (200MHz or more). Note that in order to support this
PSRAM's alignment requirements, either ahb-read-addr-opt or
ahb-prefetch must be set for the FlexSPI instance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
memc driver was setup to always assume the flexSPI would be in XIP mode,
and skip init. This is only true for the active flexSPI, which is
typically FlexSPI1. Fix this check to only skip init for FlexSPI1
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Rename flexspi-hyperram driver to flexspi-s27ks0641, and update
function names. This driver is only capable of supporting the
s27ks0641 HyperRAM chip, as the lookup table given in this driver
is specific to the s27ks0641.
Rename the flexspi-hyperram binding to reflect this, to
prevent confusion from users.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
As the unicast client, we would always create bidirectional
CIS to ensure that the PHY parameter is correctly set.
We can, however, just set the (required) PHY value and
leave the SDU and RTN values as 0, to avoid
creating bidirectional CIS.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
If either the sink or source ASE count was zero, calls to
ARRAY_SIZE(srcs) or ARRAY_SIZE(sinks) would cause a build warning.
The arrays should actually not be there at all if the respective
ASE count was 0, as that is just a waste of memory. The arrays,
and all uses of them, have been properly guarded.
This also adds a build assert to ensure that at least one
of them is non-zero, and that we also test building either
of them with the value 0.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
This allows us to allocate and bind the Audio ISO structs
to Audio Streams, thus allowing us to create the unicast group
before they have been configured.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
There was a bug in bt_audio_iso_unbind_ep that caused an
assert, missing unbinding on stream released callback
and missing state check in bt_audio_unicast_group_delete
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Printing of NACK messages should be set to LOG_DBG to avoid spamming.
When we scan whether there is a target device through I2C, if we use
LOG_ERR, it will frequently print out NACK messages. So it is set to
LOG_DBG in the case of NACK.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Fix few duplicate keys warnings in sample.yaml and testcase.yaml files,
this is going to enable some tests that were otherwise being
unintentionally ignored.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Drop duplicate entry for
logging.log_api_deferred_override_level_rt_filtering, it's already
declared with the same settings on line 106.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix a bug that causes not handling an IDLE line detection interrupt for
some STM chips, e.g. STM32F412. It impacts the async UART
communication - an information that data have been recieved is lost.
The issue occurs when the IDLE flag is set during handling another UART
interrupt, e.g Transmission complete. The ISR calls uart_stm32_err_check
function, which clears the noise error flag with LL_USART_ClearFlag_NE
without any additional checks. Unfortunately, clearing the noise flag
also clears the IDLE flag for some chips(an read to the USART_SR
register followed by a read to the USART_DR register for STM32F412
clears PE, FE, NF, ORE and IDLE flags), hence the ISR is not called
again for the IDLE event. The IDLE flag is no longer set.
Add checking the noise flag before clearing it.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Use k_work_delayable instead of k_timer in order to execute timeout in
USB workqueue context instead of ISR context. This fixes Will-Detach on
targets where usb_dc_detach() uses functions not allowed in ISR context,
e.g. nrfx usb_dc_detach() acquires mutex.
Fixes: c27d48c89a ("usb: dfu: Support DFU with WinUSB on Windows")
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
If defined(CONFIG_ASSERT) and !defined(CONFIG_ADSP_IMR_CONTEXT_SAVE),
build will fail as symbol "global_imr_ram_storage" is not defined.
Link: https://github.com/thesofproject/sof/issues/6896
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
ESP32 and ESP32-S2 HW clock are tied to DTS clock configuration.
This changes updates the default configuration to retrieve
this information from DTS.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Xtensa's ESP32 misses this base CCOUNT value, which causes wrong
arch_timing_freq_get() value reference.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
