Disable logging module in CDC ACM to prevent recursive logging loop when
CDC ACM is used as serial backend.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add support for SECO JUNO board embedded microcontroller STM32F302VC,
designed to extend capabilities of the main processor Rockchip PX30.
The microcontroller provides several interfaces, such as 2 and 4-Wire
UARTs, USB, CAN, Modbus, 8-channels Timer, SPI, I2C and GPI/Os.
The communication between the two processors is realized with an
internal SPI line.
Signed-off-by: Ettore Chimenti <ettore.chimenti@seco.com>
Add entries for the BUCK0/1/2/3 and LDO0/1 regulators. Note that voltage
min/max limits have been set to the hardware limits. They can be
adjusted using overlays in applications, depending on the consumer
circuit constraints.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Update documentation for imxrt boards to reflect the default clock
source being systick, and clarify that the GPT timer will only be
used in low power modes. Add a build time warning when the GPT
timer is enabled, so that the user will be aware of the resolution
tradeoff when using the GPT timer.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Switch all imxrt boards to use the systick timer by default, and only
enable the GPT timer when using low power modes. This is desirable
because the systick has a higher resolution, but the GPT can run
while the core clock is gated, making it useful for low power modes.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow enabling CDC ACM logging only if CDC ACM is not used as logging
backend. This prevents endless recursive logging loop, especially
visible when minimal footprint logging is enabled.
Fixes: #52981
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
PCA9420 PMIC offers of multiple operation states, or DVS (Dynamic
Voltage Scaling). Such states may be automatically changed by hardware
using MODESEL0/1 pins. Certain MCUs allow to automatically configure
certain output pins when entering low power modes so that PMIC state is
changed without software intervention. This means that application just
needs to configure the voltages for each state using
`nxp,modeN-microvolt`, set `nxp,enable-modesel-pins` in devicetree and
forget about configuring regulators.
This patch introduces a new _parent_ API to expose such functionality in
a vendor agnostic way. Consider this API as experimental for now, until
we have other usecases.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Most of devicetree properties for regulator, such as:
- regulator-min/max-microvolt
- regulator-min/max-microamp
- regulator-allowed-modes
- etc.
Are meant to specify limits on what consumers may set. They are **NOT**
meant to describe the hardware capabilities. For example, I could have a
BUCK converter that supports 0-5V output voltage, but my circuit may
only allow working on the 2.7-3.3V range.
This patch reworks the API so that the API class layer manages this
information. This is done by drivers collecting all such fields in a
common configuration structure that is later accessed by the class
layer. This simplifies drivers implementation. For example, if A
consumer calls regulator_set_voltage() with a voltage that is supported
but not allowed, driver code won't be called. Similarly, if a regulator
is configured to be `always-on`, enable/disable driver code will never
be called.
Drivers have been adjusted. PCA9420 mode settings have been removed from
devicetree in this commit as they are not actual modes but PMIC states.
This will be refactored in a follow-up commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In some simulated test cases, it can be usefull
to delay the boot of the CPU and the test initialization
for a while. Namely by the offset of the device
relative to other simulated devices.
We add the option to select so from command line.
By default the option is disabled so this change is
backwards compatible.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Add board files and documentation for mec172xmodular_assy6930.
This is for MEC172x Modular Card support.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Enables the HSI48 clock on the nucleo_g0b1re platform.
Fix warning when building USB related samples.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The XY Memory is a feature commonly found in DSP processors to increase
the DSP performance. The XY component allows a ARC processor to
implicitly load source operands and store results into a closely coupled
memory using a single instruction.
Add XY memory for ARC EM9D/EM11D processors including em_starterkit,
em_starterkit_em11d. emsdp_em9d, nsim_em, iotdk.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.
This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.
The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Add DTS information for qemu-virt-a53 and qemu-kvm-arm64 for PCIe
controller support. Three new bindings are required for the PCIe
controller in ECAM mode.
The DTS information was extracted from QEMU (dumpdtb) with a PCIe device
attached to the virtual machine (ivshmem)
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Now that we have support for the GPIO and pinctrl APIs on this platform,
enable them by default and add definitions for the on-board LEDs and
switches. Additionally, use the pinctrl API to configure the UART pins.
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
The shell UART in the chosen node was incorrectly specified as
"zephyr,shell" instead of "zephyr,shell-uart". Fix it.
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Add configuration for built-in display.
LCD has a Sitronix ST7735S controller that is connected to the SPI bus.
Using it with the ST7735R driver.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Adds support for the Adafruit ItsyBitsy nRF52840 Express.
This board ships with the UF2 bootloader, so the device has
been set up so that Zephyr applications are flashed the
same way that other (Adafruit) firmware is flashed with the
UF2 bootloader.
This has been tested locally, and the button, blinky and
led_apa102 samples run without problems.
Signed-off-by: Embla Flatlandsmo <embla.flatlandsmo@gmail.com>
The different boards with stm32 which have node enabled in their DTS
also requires the HSI48 clock to be enabled.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The different boards with stm32 which have node enabled in their DTS
also requires the HSI48 clock to be enabled.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The different boards with stm32 which have node enabled in their DTS
also requires the HSI48 clock to be enabled.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The nucleo_wb55rg platform has Bluetooth feature that
requires the HSI48.
The board DTS enables the HSI48MHz clock for that purpose.
And also selects it as the source (default) of the CLK48.
Note that the clk48 node must be enabled for any another source.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add support for loading M4 image from OCRAM when running with dual core
operation. The M7 core will copy the M4 image from flash into OCRAM, and
the M4 core will execute it there.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Flexspi partition definition is shared between both cm4 and cm7 core.
Refactor it to be in shared dtsi file. This will ensure that both cores
share the same partition information, for dual core operation.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable the openamp sample for RT1170EVK. CM4 core has a custom DTS
overlay to use LPUART2 for console information, and use a secondary GPT
timer for the system tick.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for loading M4 image from OCRAM when running with dual core
operation. The M7 core will copy the M4 image from flash into OCRAM, and
the M4 core will execute it there.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Flexspi partition definition is shared between both cm4 and cm7 core.
Refactor it to be in shared dtsi file. This will ensure that both cores
share the same partition information, for dual core operation.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT1170 and RT1160 CM7 and CM4 cores have the same set of differences.
Merge the DTS files for both CM4 and CM7 cores, to create generic
rt11xx_cm4 and rt11xx_cm7 files.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
- Similar to what was done for other parts of the driver, remove any
register specification from Devicetree (modesel-reg/mask)
- Keep all the information in the driver, and define modes as "numbers",
e.g. PCA9420_MODE0: 0, PCA9420_MODE1: 1, etc.
- Bindings provide IC defaults now (all modes allowed 0/1/2/3 and
initial mode set to 0).
- When mode is controlled via the MODESEL0/1 pins (ie directly by an iMX
MCU using the dedicated PMIC_MODE0/1 pins), the driver will not allow
to select a mode (it is not possible). This mode is now enabled by
setting `nxp,enable-modesel-pins` in Devicetree. When enabled, all the
allowed modes are configured to be selectable via pins. When disabled,
mode can be set via I2C (using TOP_CNTL3 MODE0/1_I2C fields)
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
