Commit graph

4 commits

Author SHA1 Message Date
Sylvio Alves
4b5331ba45 linker: esp32: move snippets-section within rom boundary
This will guarantee that application snippets will be placed
into ROM section properly.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-10-13 13:10:22 +03:00
Sylvio Alves
f5fa4b3bcd soc: espressif: provide VMA to rodata and text by default
Flash segments require VMA to proper work. Executing from LMA
is not possible. Current implementation did not take into account
runtime iterable rom sections that any application could implement.
In the above cenario and as reported in the issue below, ESP32 won't run
when those ROM sections are created in application level.

This change make sure all flash segments are properly mapped
accordingly.

Fixes #61834

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-09-18 10:38:03 +01:00
Almir Okato
af3b04238e soc: espressif: adjust memory organization on linker
Adjust the memory organization to avoid overlapping
critical regions from bootloaders (MCUboot and IDF)

Signed-off-by: Almir Okato <almir.okato@espressif.com>
2023-08-31 14:08:41 +02:00
Marek Matej
6b57b3b786 soc: xtensa,riscv: esp32xx: refactor folder structure
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:

- changing the CONFIG_SOC_ESP32* to refer to
  the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
  the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
  provide a SOC model config
- introducing the 'common' folder to hide all
  commonly used configs and files.
- updating west.yml to reflect previous changes in hal

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-25 18:12:33 +02:00
Renamed from soc/riscv/esp32c3/default.ld (Browse further)