With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.
Redirects for the web documentation are also included.
Then zephyrbot complained about this:
"
New files added that are not covered in CODEOWNERS:
dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi
Please add one or more entries in the CODEOWNERS file to cover
those files
"
So I assigned them to those who created them. Feel free to readjust
as necessary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
1. Add flash partitions.
2. Add macro DT_START_UP_ENTRY_OFFSET. The entry of the RV32M1 is
not the start of the vector table. Add the macro to inform the
entry offset.
3. Update linker file to support MCUboot
a. For normal cases (CONFIG_BOOTLOADER_MCUBOOT is cleared), the
vector table is located last 256bytes of the flash.
b. If CONFIG_BOOTLOADER_MCUBOOT is set, the vector table is located
after the image header of MCUboot.
Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
Allows snippets to be placed in different locations:
- The noinit, rwdata and rodata output sections
- Two different locations for placing custom output sections,
one location for RAM and another for all other sections.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
Moves the flash memory definitions from Kconfig to device tree for the
rv32m1 ri5cy and zero-riscy cores.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Moves the sram memory definitions from Kconfig to device tree for the
rv32m1 ri5cy and zero-riscy cores.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Apply a similar fix to commit 0289a410ba
to the openisa_rv32m1 linker script for handling .srodata sections.
Otherwise we get oprhan read-only data section. Fix this by adding
the .srodata section to the RISC-V linker script.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V
32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two
cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC
enablement for the RISC-V cores:
- basic dtsi, to be extended as additional drivers are added
- SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY
- system timer driver for RI5CY, based on LPTMR0 peripheral
The timer driver will be generalized a bit soon once proper
multi-level interrupt support is available.
Emphasis is on supporting the RI5CY core as the more capable of the
two; the ZERO-RISCY SoC definitions are a good starting point, but
additional work setting up a dtsi and initial drivers is needed to
support that core.
Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Michael Scott <mike@foundries.io>
