soc: riscv32: Move rv32m1 flash memory definitions to dts
Moves the flash memory definitions from Kconfig to device tree for the rv32m1 ri5cy and zero-riscy cores. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
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7 changed files with 75 additions and 15 deletions
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@ -14,6 +14,7 @@
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chosen {
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zephyr,sram = &m4_dtcm;
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zephyr,flash = &ri5cy_code_partition;
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zephyr,console = &uart0;
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zephyr,uart-pipe = &uart0;
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};
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@ -14,6 +14,7 @@
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chosen {
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zephyr,sram = &m0_tcm;
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zephyr,flash = &zero_riscy_code_partition;
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zephyr,console = &uart0;
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zephyr,uart-pipe = &uart0;
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};
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@ -280,5 +280,30 @@
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#size-cells = <0>;
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status = "disabled";
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};
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flash-controller@40023000 {
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compatible = "nxp,kinetis-ftfe";
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label = "FLASH_CTRL";
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reg = <0x40023000 0x18>;
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#address-cells = <1>;
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#size-cells = <1>;
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m4_flash: flash@0 {
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compatible = "soc-nv-flash";
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label = "M4_FLASH";
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reg = <0 0x100000>;
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erase-block-size = <4096>;
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write-block-size = <8>;
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};
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m0_flash: flash@1000000 {
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compatible = "soc-nv-flash";
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label = "M0_FLASH";
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reg = <0x01000000 0x40000>;
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erase-block-size = <4096>;
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write-block-size = <8>;
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};
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};
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};
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};
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@ -16,6 +16,29 @@
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};
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};
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&m4_flash {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* This configuration assumes the Arm cores are disabled, as
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* these base addresses contain the Arm core vector tables if
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* they are used.
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*/
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ri5cy_code_partition: partition@0 {
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label = "ri5cy-code";
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reg = <0x00000000 0x000fff00>;
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};
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ri5cy_vector_partition: partition@fff00 {
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label = "ri5cy-vector";
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reg = <0x000fff00 0x100>;
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};
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};
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};
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/*
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* INTMUX channels below are somewhat arbitrary.
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*
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@ -16,6 +16,29 @@
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};
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};
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&m0_flash {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* This configuration assumes the Arm cores are disabled, as
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* these base addresses contain the Arm core vector tables if
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* they are used.
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*/
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zero_riscy_code_partition: partition@1000000 {
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label = "zero-riscy-code";
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reg = <0x01000000 0x0003ff00>;
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};
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zero_riscy_vector_partition: partition@3ff00 {
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label = "zero-riscy-vector";
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reg = <0x0003ff00 0x100>;
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};
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};
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};
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/*
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* INTMUX channels below are somewhat arbitrary.
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*
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@ -49,19 +49,6 @@ config RISCV_SOC_INTERRUPT_INIT
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config WDOG_INIT
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def_bool y
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# Built-in flash allocated to each chip. This configuration
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# assumes the Arm cores are disabled, as these base addresses
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# contain the Arm core vector tables if they are used.
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config RISCV32_RV32M1_ROM_BASE_ADDR
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hex
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default 0x00000000 if SOC_OPENISA_RV32M1_RI5CY
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default 0x01000000 if SOC_OPENISA_RV32M1_ZERO_RISCY
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config RISCV32_RV32M1_ROM_SIZE
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hex
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default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY
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default 0x0003FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY
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# The event unit looks for vector tables at the end of each core's
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# flash space. These vector tables are not relocatable.
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config RISCV32_RV32M1_VECTOR_BASE_ADDR
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@ -29,8 +29,8 @@
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#define ROMABLE_REGION ROM
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#define RAMABLE_REGION RAM
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#define ROM_BASE CONFIG_RISCV32_RV32M1_ROM_BASE_ADDR
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#define ROM_SIZE CONFIG_RISCV32_RV32M1_ROM_SIZE
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#define ROM_BASE DT_FLASH_BASE_ADDRESS
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#define ROM_SIZE KB(DT_FLASH_SIZE)
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#define RAM_BASE DT_SRAM_BASE_ADDRESS
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#define RAM_SIZE KB(DT_SRAM_SIZE)
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#define VECTOR_BASE CONFIG_RISCV32_RV32M1_VECTOR_BASE_ADDR
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