Several issues:
- `last_count` should not be updated with current time or this will
cause a time drift and induce jitter due to IRQ servicing latency.
- `sys_clock_set_timeout()` should not base its `mtime` on the current
time either. Tracking the `last_tick` and `last_elapsed` values avoids
the need for all the tick rounding computation.
- The MIN_DELAY thing is pointless. If the delay gets close or even behind
current time then the IRQ will be triggered right away. This is unlikely
to happen very often anyway so the constant overhead is uncalled for.
- Runtime 64-bits divisions on 32-bits hardware are very expensive.
Fix the above, and improve the following:
- Prime the accounting by simply invoking the IRQ handler from the init
code. That will make the "ticks since boot" counter right.
- Remove excessive casts, especially a few wrong ones.
- Simplify the code overall.
Here's the output from the timer_jitter_drift test.
Before this patch:
|timer clock rate 60000000, kernel tick rate 10000
|period duration statistics for 10000 samples (0 rollovers):
| expected: 1000 us, 60000.000000 cycles
| min: 907.600000 us, 54456 cycles
| max: 1099.750000 us, 65985 cycles
| mean: 1008.594633 us, 60515.678000 cycles
| variance: 2.184205 us, 7863.136316 cycles
| stddev: 1.477906 us, 88.674332 cycles
|timer start cycle 995589, end cycle 606152369,
|total time 10085946.333333 us, expected time 10000000.000000 us,
|expected time drift 0.000000 us, difference 85946.333333 us
After this patch:
|timer clock rate 60000000, kernel tick rate 10000
|period duration statistics for 10000 samples (0 rollovers):
| expected: 1000 us, 60000.000000 cycles
| min: 992.116667 us, 59527 cycles
| max: 1030.366667 us, 61822 cycles
| mean: 1000.001902 us, 60000.114100 cycles
| variance: 0.105334 us, 379.201081 cycles
| stddev: 0.324551 us, 19.473087 cycles
|timer start cycle 987431, end cycle 600988572,
|total time 10000019.016667 us, expected time 10000000.000000 us,
|expected time drift 0.000000 us, difference 19.016667 us
The mean, variance and standard deviation number differences speak for
themselves, even in the absence of competing ISRs and/or IRQ-disabled
periods which would have made the comparison even worse.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Update machine timer drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on NIOSV devicetree.
Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
`#defines` do NOT sepecify a type. They will either adopt a native
system type or type of the value that was passed into the expression.
This can lead to warnings such as, "warning: comparison of integer
expressions of different signedness: 'uint32_t' {aka 'unsigned int'}
and 'int' [-Wsign-compare]".
By casting expressions, such as `MAX_TICKS` to `k_ticks_t`, we can
force the appropriate types and resolve these warnings.
Signed-off-by: Zachary J. Fields <zachary_fields@yahoo.com>
This is a follow-up to commits cf871aec64
and 205e684958.
It turns out that the current implementation of the nrf_rtc_timer may
still fail to properly handle a timeout if that timeout is set in very
specific conditions - when a previously set timeout is about to expire.
When that happens, the new timeout is handled 512 seconds later (when
the system timer overflows) than it should be.
A recently added nrf_rtc_timer test case (test_tight_rescheduling)
exposes this problem and this commit fixes it by adding examination
of COMPARE events that appear during setting of the CC register value
for a given timeout.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This function name is misleading as the absolute time values handled
by the driver are 64-bit and this function receives a 32-bit parameter,
which is supposed to be a CC register value, not the target time.
Correct the name of this function and its parameter, and remove a now
unnecessary masking from its body.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
On the stm32U5, when modifying the DIER register of the LPTIM peripheral,
a new write operation to can only be performed when the previous write
operation is completed and before going-on.
This is done with a function call for better readability.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The introduction of cc2c05a90c caused
CONFIG_MCUX_LPTMR_TIMER to always be enabled for boards where the NXP LPTMR
is enabled in the board devicetree.
Using this low-power timer as system timer only makes sense when using
power management. Otherwise, it just results in a lower tick resolution and
non-tickless operation.
Add dependency on CONFIG_PM for CONFIG_MCUX_LPTMR_TIMER.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
It is not guaranteed that a multi-core RISC-V hart numbering scheme
will match Zephyr's sequential cpu numbering scheme. Read the hartid and
use that value in calculation to get mtime_cmp reg, instead of the
current_cpu id.
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
This is a follow-up to commit 205e684958.
The recently added nrf_rtc_timer test case (test_next_cycle_timeouts)
revealed a problem in the current implementation of this function.
Adjust it to avoid missing COMPARE events in specific circumstances.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add dependency on SYS_CLOCK_EXISTS to all timer configurations.
This would avoid a situation where a possible timer configuration would
be wrongfully selected but SYS_CLOCK_EXISTS is disabled.
This simplifies code that wants to check for system clock capabilities
don't have to check if the system clock exists in addition.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
There is no need to disable interrupts while just checking if
a channel needs to be processed in the ISR, as that section
does not contain anything that needs to be protected against
overwriting from some other context. In particular, if a given
timeout is changed or even aborted while its event is being
checked, this will be correctly handled in the code that follows
and that checks the expiration time.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Values to be set to the comparator need to be specified in RTC cycles,
not ticks, so the initial value used in the tickless mode needs to be
MAX_CYCLES, otherwise when CONFIG_SYS_CLOCK_TICKS_PER_SEC is set to
a value less then the RTC frequency, the initially configured timeout
will be unnecessarily shorter.
On the occassion, remove also the call to counter() when setting the
initial timeout value in non-tickless mode. RTC is cleared a few lines
above, so at this point it will most likely be 0, and even if it was
not, compare_set() would properly handle a target time value that had
already passed.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
In non-tickless mode, the timeout handler always announced maximum 1
tick to kernel, but in fact it cannot be guaranteed that the handler
execution is not delayed and that the number of elapsed ticks does not
exceed 1. Use the actual number instead.
Switch also to using a 32-bit value for `dticks` to get a bit simpler
generated code (ticks delta is not supposed to be that huge).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Align the condition checked in compare_set_no_locks() with what
set_absolute_alarm() actually provides (and slightly correct the
latter function so that it provides what it is supposed to).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add missing masking against `BIT(chan)` when handling a forced ISR
to avoid unnecessary processing of multiple channels instead of just
the one that actually requires it.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Remove a piece of code that was supposed to bring an extra update
of the anchor value but which in fact was not able to provide it,
because of the target time checking performed in process_channel(),
and which is anyway unnecessary because the timeout span is limited
to MAX_CYCLES in sys_clock_set_timeout(), so the timeout handler is
guaranteed to be executed at least twice per each RTC overflow.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Eliminate waiting for a potential COMPARE event when setting a CC
value close to the previously set one and rely instead on checking
target time when processing channel events in the ISR.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Remove unnecessary decreasing of the number of ticks by 1 (it was then
increased by 1 when it was converted to the number of cycles) and add
a comment that clarifies the way that ticks < 1 are handled.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The stm32 devices shows a x2 factor on the LPTIM1,3,4
clock source but it acts as a prescaler.
The max lptim counter (timebase) is counting 4 sec
In that case, the LPTIM count unit is double.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
hal_espressif systimer HAL calls are based on 1MHz reference.
This changes systimer driver to allow max clocking reference of 16MHz
and increases soc tick resolution by reducing min delay interval.
This also sets all ESP32-C3 socs to 16MHz hardware cycles reference.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Bug occurs when polling kernel uptime. Uptime was suddenly
jumping because lptim counter was counted twice
(from CNT and ARR registers) in case reload happens between
values are fetched.
Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
Switch all imxrt boards to use the systick timer by default, and only
enable the GPT timer when using low power modes. This is desirable
because the systick has a higher resolution, but the GPT can run
while the core clock is gated, making it useful for low power modes.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RTC is 24 bit width and k_timer is 64 bit. It is hard to test corner
cases but RTC hardware feature can help here. There is a task which
moves counter to 0xfffff0 which is close to overflow. However, there
is an internal driver state that also needs to be aligned to shift
the time properly. Adding optional function which triggers overflow
and updates internal state. This can be used for testing corner cases.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
CC setting algorithm is handling a case when CC is too soon (next
tick from now). It was setting CC to one tick further in the future
if that was detected. Step was repeated if counter incremented during
setting CC and CC was behind the counter because of risk of setting
CC too late. In certain scenarios we might spend a lot of time in
that loop, especially if optimization is turned off. Test shown that
loop was executed dozens of time (up. to 700us). To prevent
prolonged execution whenever CC setting fails we set CC to one more
tick further in future.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This seems to have caused CI failures and its unclear why just yet
so revert instead.
This reverts commit cbee9e9fdd8060d0ca4e91037b3f99f631e4b1a5.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Update Intel ADSP timer driver to use DT_HAS_<compat>_ENABLED Kconfig
symbol to expose the driver and enable it by default based on
devicetree.
We remove setting 'default y' for the timer driver in
Kconfig.defconfig.series as that is now handled in the driver Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Mark the timer as having a lock free read of the cycle count
so that spin lock debugging can include lock time asserts.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Selects the hidden Kconfig to note that the APIC timer's cycle count
accessor is a lock free path and may use the spin lock time limit check.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Select the Kconfig option noting that the cavs (intel adsp)
timer driver provides a lock free cycle count accessor and
therefore can be used with a spin lock time limit assert.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Spin locks held for any lengthy duration prevent interrupts and
in a real time system where interrupts drive tasks this can be
problematic. Add an option to assert if a spin lock is held for
a duration longer than the configurable number of microseconds.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
For 32 bit processor to read the 64 bits hpet counter, the HPET spec
2.4.7 suggest to read HPET counter high and low then checking the
high bits to decide if it rollovers or not.
But this logic seems to cause problem for 64 bits processor under SMP,
there is a possible one tick earier under tickless mode. It is likely
to be the cache coherence issue, because a mfence instruction before
reading the timer works.
So we change to read the 64 bits counter by sys_read64 on 64bit
processor to prevent this issue.
Fixes#49611
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
File still not being removed due to out-of-tree usage. We will drop it
once the external code has stopped referencing it.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Convert timer driver to use a light weight syscon and DTS and convert
register information to use offsets and sys_read/sys_write instead of
structs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Cleanup soc.h and move interrupt defines into own headers. Rename some
of the defines for ACE to have a unified namespace.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The DW register block was duplicated into the ACE header while we had
the same thing in the driver. Move everything to the driver as the first
step with further improvements planned on top of this.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some headers made use of types defined in sys_clock.h (e.g. k_timeout_t)
without including it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files using time_units.h API did not include it, e.g. for
sys_clock_hw_cycles_per_sec.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The sys* ops like sys_clear_bit are indirectly included via arch CPU
header. Other stuff like find_msb_set end up included via this header as
well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
It is better to use 64-bit variable types for calculating the number
of elapsed ticks than 32-bit variable types. This guards against the
propagation of calculation errors should the lower 32-bits of the timer
counter roll over multiple times before the timer ISR is serviced.
(Such a scenario can easily occur when pausing the system for an
extended period of time with a debugging device such as a Lauterbach.)
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
