NPCX watchdog driver has a WDT_NPCX_DELAY_CYCLES for delay the watchdog
reset time after the watchdog timeout. For some systems, users would
like to use the watchdog timeout ISR but don't reset the chip
immediately. Let the system have the final chance to ongoing the system
before the real hardware reset time. Removing the watchdog reset
waiting loop in ISR lets users decide whether wait for watchdog reset
by themself.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Register T0CSR bit 4 is WDRST_STS which is used to check whether the
chip has watchdog reset from the last power-up or vcc1_rst. WDRST_STS
hardware is design to write one clear. For the original
read-modify-write, it will reset the WDRST_STS unexpected. Add a mask
to avoid it.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
In npcx7 series, the Timer and Watchdog module (TWD) generates the
clocks and interrupts used for timing periodic functions in the system.
It also provides watchdog reset signal generation in response to a
failure detection.
The CL also includes:
— Add npcx watchdog device tree declarations.
— Zephyr watchdog api implementation.
— Add Watchdog definitions for npcx7 series in
tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c for
supporting test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
