Adds a new uart_irq_tx_empty function in the UART base API.
Change-Id: Iab76251d4d40b92a553628956c49f1dd707292b5
Signed-off-by: Fabien Chereau <fabien.chereau@intel.com>
Adds a new uart_err_check function in the UART base API.
Change-Id: Ia94386d75fcb66a582a2ad919c1a7afb05dd7776
Signed-off-by: Fabien Chereau <fabien.chereau@intel.com>
Updates the sanitycheck script to identify the "init_array" section
as a valid section in the image.
Change-Id: I55c20909d3734e68e8ec319e1abde94da93665a1
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Updates the minimal libc headers for differences between the C and C++
languages. This includes ...
1. Conditionally defining "bool", "true" and "false" as they are
already keywords in C++.
2. Making the definition of NULL language dependent.
3. Using the _Restrict macro instead of the restrict keyword as
restrict exists in C, but not in C++.
4. Changing the definition of size_t so that it is compatible with
what the compiler expects when building the new operator stubs
(as it varies by architecture).
Change-Id: I37ff058a60b90a05f96e9dd6f61d454d143041ce
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Consolidates the definitions of size_t in the minimal libc library.
This prevents code duplication.
Change-Id: I996990ad9093ebec1f9ba0045d14319e1a243e70
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Consolidates definitions of NULL in the minimal libc library.
This prevents code duplication.
Change-Id: Ia4a2bde1329d66e7c83afeab806a39b22704ab48
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The TASK_ENTRY_CPP macro is to be used to tag task entry points when
they are defined in a C++ file.
Change-Id: I213965cf55648f54972e1e95bf5b4269f03fd44d
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The EXTERN_C macro is to be used to ensure compatibility between C and C++;
It prevents name mangling in C++ environments.
Change-Id: I33be727150687901f7770306c8a07c16a7e46ffa
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds extern "C" { } blocks to header files so that they can be
safely used by C++ source files.
Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Introduce the GPIO QMSI-based implementation. This is basically a
shim layer that implement's Zephyr's GPIO APIs on top of QMSI drivers.
This is an alternative driver that conflicts with the previous
GPIO_DW implementation. In order to enable it you must set:
- CONFIG_GPIO=n
- CONFIG_GPIO_QMSI=y
- CONFIG_GPIO_0=y
- CONFIG_QMSI_DRIVERS=y
- CONFIG_QMSI_INTALL_PATH="PATH_TO_QMSI"
Note that this driver currently only supports one controller instance,
GPIO_0. It is implemented this way due to a limitation from the current
version of QMSI. QMSI versions later than 1.0 doesn't have this
limitation.
Missing:
- support multiple controller instances (gpio_0, gpio_1, etc);
- enable level triggered interrupts in sync with system clock,
through setting INT_CLOCK_SYNC properly.
Change-Id: Ib61b153dae9741806a9a31d7dc1f82b96d000fbe
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This commit changes the behavior of the driver when it reports
buffer results back through the callback.
Originally, the driver reported a callback after each sequence
table round signaled by an interrupt. If in repetitive mode,
each reported result was put in the next buffer element,
which was considered circular, and reported back with callback.
Now the behavior changes. If in repetitive mode, each sequence table
round reported by an interruption puts the data in next element of
the reception buffer. The callback reports back once the buffer is
fulled and stops the sampling process.
Change-Id: I3707574cfaf5dfc874473f38c5dfa88dd392133d
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
On Curie SoC the ADC must always be configured in single ended mode.
Change-Id: Ie59b4180358153865c961b66f98321db60d4269f
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
- Sample application now pulls data continuously.
- Adds information on the arduino analog input pins and ADC channels.
- CHANNEL is defined as a macro.
- BUFFER_SIZE is defined as a macro.
- Sets the sample to run on repetitive mode on ARC architectures
(applies to Arduino 101 ADC).
Change-Id: I6201fea3a98b5394c05eb3ac570793629431ac02
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
After exiting a deep power down mode a dummy conversion is required.
Change-Id: I98dad19e168984efe7af6ad360d0cc46e6603736
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Curie specs states that the ADC_PWR_MODE_STS bit in the
IO_CREG_SLV0_OBSR register must be polled to check if
the requested power mode equals the current power mode.
The bit is set to 1 when requested and current modes match
and the bit is located as the bit 0.
Change-Id: I030d7693d36fb96f09a9cbdd404118674fcb089a
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
ADC DW IP requires a calibration process each time the
IP recovers from a deep power down mode.
Change-Id: I2e02d1987af9addd9cb08a4e4e8d3848ad5b623c
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
This patch removes the checks related to CONFIG_CC_STACKPROTECTOR_
REGULAR and CONFIG_CC_STACKPROTECTOR_STRONG options since these
options don't exist in Zephyr. According to 186ab6552, they were
copied from Linux but further clean up was missing.
Change-Id: I1d8b4f47319a54b68b6f0b5aec1feb0a247e72e9
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
It wasn't immediately clear in _execute_handler() that
enable_interrupts() didn't actually do anything if
CONFIG_NESTED_INTERRUPTS wasn't enabled.
If we are not using nested interrupts, perform small optimization
1) The call to disable interrupts isn't necessary as interrupts
are already disasbled
2) The check for !_nanokernel.nested in a couple places always
evaluates to true if nested interrupts aren't used
Change-Id: I7e66cee0466d03bc1172a572e19389accf6e0e62
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
On NANOKERNEL level only of course. Some devices, initialized at this
level, may require to get the clock running already.
Change-Id: Id2dd830d915474aac6c080068c2cf356cf841e0c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Controller should not be enabled while configuring or setting up a
transfer call. It's enabled once the transfer call is ready to proceed,
and disabled once the last interrupt has be raised.
Change-Id: Ib9125a3600971b57e642730682f2b3bfb91b1e02
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
On Quark SE, SPI might require GPIO to be ready before hand, to emulate
CS, thus providing an option to tweak the intialization priority for SPI
DW driver.
Change-Id: Ifa373948ac8227bf6e4ed1113bcb4dc9139b6663
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
It might be necessary to emulate CS through a GPIO pin depending on
these 2 conditions:
- the controller's CS pin is not wired, and thus a GPIO pin is the only
option
- The controller is unstable at a certain frequency and cannot set/unset
CS reliably. This is actually a possible issue on DesignWare's SPI
controller in Quark SE or Quarks D2000 where it has been found
unstable at 1Mhz and above.
Change-Id: Ib6a06577906c005ddd347070d476a367a9c3da8a
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
- Refine how DFS is calulated now that it is strictely used to
manipulate buffer lengths.
- Fix threshold limit
- Tune RX threshold relevantly (reduce it if rx_len is lower than actual)
- Don't push more than available left space in FIFO
- Tune the private structure to lower memory space occupation
Change-Id: I65b1b48b996b2104cebcb24cc366fb4dcbf7d53b
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
IMR and ISR bits are same, but it stil better to differentiate them
properly. Also fixing naming where all ISR ends with an 'S'.
Change-Id: I2fc1e1d8d2743c3d98f5da40a5f4720a85c4f9a7
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
On ARC, the SPI IP block might be accessible only via user extended
auxiliary registers, which requires different instructions to read from
and write to.
Change-Id: I3aa5f223938a9aed7795de4aedc64bd529d62942
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Registers offsets are hopefully all the same, but size differs.
On x86, thus 32bits support, CTRL0 or DR for instance are 32 bits r/w.
And DFS on 32 bits support is placed differently as well.
Change-Id: I5115d5c3c9bba71ece4a6f4a1d3d2fdc203c8da1
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Only 8 bit frames were supported. Added support for bigger data frames
which can go up to 32 bits (on 32bits version of the controller, 16 bits
otherwise). Store the frame size in bytes during configure, and use it
during pull/push to read/write correct frame size.
Change-Id: Iae8c55442e0a205403aa3febd1811b36aaf4c5b6
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
If SPI_INTEL is not requested, no need to instanciate specific value.
Change-Id: I5f41d919e258e420f2bd099db88ed2259f9cd27e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Reported by Ramesh Thomas, the loop mode is included in the mode
configuration and not as a standalone bit. Also rewording word_size
parameter documentation.
Change-Id: I1e3337087316f56d58e843278b9c65e9f4f5476f
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Quark SE SS provides 2 valid GPIO controllers, thus enabling the built
test case for it.
Change-Id: I46c6ceb3d4fe78a87c095e24851d289720524a9c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Enable both controllers by default if GPIO is enabled, providing all the
necessary information.
Change-Id: I5aab00324b10492eefb67e9595da491775cbd95d
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There is no such thing as "IA" in Quark SE SS as it is an ARC core. Plus
for this very specific feature it does not require the ARC aux regs
instruction to read/write in the given mask address.
And fixing also the CONFIG_ option to check.
Change-Id: I1f63348ec85f6e006795f7641c912a30fc003709
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Quarks SE owns a GPIO controller which is always on (so not clock-gated)
thus providing it base address, the pins it handles etc...
Change-Id: Ifceb7cb74e763a91130d615ba19756ddcbe97a23
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This is valid only for Quark SE and Quark SE SS, where it requires to
unmask the interrupt for each specific controller. Thus making the
function generic, using the parameter as the specific mask base address.
Change-Id: Iea0a412b8d94a1ab5e1f3e339eaf632eacee5797
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
We can save a great deal of RAM this way, it only needs to be
in RAM if dynamic interrupts are in use.
At some point this config option broke, probably when static
interrupts were introduced into the system.
To induce build (instead of runtime) errors when irq_connect_dynamic()
is used without putting the table in RAM, the dynamic interrupt
functions are now conditionally compiled.
Change-Id: I4860508746fd375d189390163876c59b6c544c9a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is a sample app to interface with TI INA219 power monitor.
The values used in the app are for use on Adafruit's breakout board
(https://www.adafruit.com/products/904).
This assumes the slave address is 0x40, where A0 and A1 are all
tied to ground.
Change-Id: I4116629171a98be6f2b9aa422dd3eb386b4d59c2
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The original value of 128 was selected more or less randomly, and
isn't sufficiently large enough for QA needs.
Change-Id: I8a9fcc86d6b5fa7dc5ba05896c62f7dd608f9ed2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Updating the SDK version to 0.7.1 and the download link for it.
Change-Id: I63c4d57fdc96f60426af8610c7f9ac69e79fe69c
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
This adds very basic support for running on Arduino Due.
Only the nanokernel hello_world has been tested.
Change-Id: I42b83d7f23ff88f709d2d6f2d43c6d29c82b9d32
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds driver for the UART controller on Atmel SAM3X8E.
This UART controller only has two wires for RX and TX, and
does not have flow control (e.g. CTS, RTS) or FIFO.
Currently, the driver does not support any interrupt driven
operations.
Change-Id: I63720bccfb70a89888353b8ee3dfc4b80793dc01
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds initial support for Atmel SAM3X8E processor, which is
based on ARM Cortex-M3. The SAM3X8E is being used on Arduino Due.
Change-Id: I199efcf29629f9ebacad474e5edc91bc3757f613
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
