Add api to raise SGI to target cores in affinity level identified
by MPIDR. Currently only EL1S is supported.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
The front side bus interrupt delivery feature is a somewhat obscure
part of PC history (in some sense a presaging of MSI interrupts) that
we don't use.
But it's part of the spec, works on hardware, has precedence over the
"legacy" interrupt routing feature we do use, and can be legally
enabled by firmware.
Disable at init time.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There is a typo in the function pointer assigned to get_parameters. It
should be flash_sam_get_parameters.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
It is desired to have the peripheral writes completed to clear the
interrupt condition and de-assert the interrupt request to GIC before
EOI write. Failing which spurious interrupt will occur.
A barrier is needed to ensure peripheral register write transfers are
complete before EOI is done.
GICv2 memory mapped DEVICE nGnR(n)E writes are ordered from core point
of view. However these writes may pass over different interconnects,
bridges, buffers leaving some rare chances for the actual write to
complete out of order.
GICv3 ICC EOI system register writes have no ordering against nGnR(n)E
memory writes as they are over different interfaces.
Hence a dsb can ensure from core no writes are issued before the
previous writes are *complete*.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Right now we depend on NEWLIB_LIBC to build Zephyr with LORA=y. This
seems to be the only Kconfig option like that. Convert it to select
REQUIRES_FULL_LIBC instead, which will select NEWLIB_LIBC by default and
allow to use external libc as well.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
In sensors drivers, in gpio callback function :
The device structure in parameter is related to the gpio device.
Signed-off-by: laurence pasteau <laurence.pasteau@stimio.fr>
Commit id a538dcd8f8 got rid of the usage of these pointers so they are
useless now and can be removed in this drivers.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Convert the present initialization code into initialization macros.
Since both the uart and the usart peripheral is implemented, two sets
of initialization macros are necessary.
Signed-off-by: Christian Taedcke <christian.taedcke@lemonbeat.com>
Parsed value is expected to be in range (0, UINT32_MAX). Use strtoul
instead of strtoll, so we better match its range. In a tested
configuration this saves 380 bytes of flash with newlib and arm32
target.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
This enables the ACPI_EC1 interface which is typically accessed
through ports 0x6A0 and 0x6A4 in Bios.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
For some reason, use of the DT_NUM_INST macro in this driver was not
replaced with DT_NUM_INST_STATUS_OKAY. In consequence, this driver
could not be compiled successfully. Furthermore, because this now
undefined macro had been used inside UTIL_LISTIFY, gcc was not even
able to report an error, instead the compilation just "froze".
This patch replaces UTIL_LISTIFY(DT_NUM_INST()) with more appropriate
in this context DT_INST_FOREACH_STATUS_OKAY. It also adds an apparently
missing inclusion of sys/byteorder.h.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
pcie has an all in one command for listing pci devices. Make it support
additional commands and move lspcie to `pcie ls`.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
If shell is enabled then enable all sub-shells if their dependencies are
satisfied. This was done for some modules and subsystems but was not
consistent.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Printing the file descriptor does not give any information when
the network interface creation fails, so print errno here instead.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
The driver was returning zero due to accessing the, say, 0x81'th
endpoint instead of the 0x01'th endpoint.
Signed-off-by: Michael Hope <mlhx@google.com>
Espi has three uart port from 0 to 2 and uart sirq need to enabled for
the port which is active in the hardware. An active uart sirq shoudl be
enabled based on uart mapping configuration.
Signed-off-by: Venkataramana Kotakonda <venkataramana.kotakonda@intel.com>
All pinmux supporting CAN, SPI and I2C of F7 series are added.
Since the F7 series supports up to two CANs,
the pin names of CANs have been changed.
Several minor pinmux errors have also been fixed.
Sorted by Alternate function.
Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
Avoid reading LPTIM counter four times instead of three when second
read doesn't give same value. Use common code, avoid volatile for
local vars.
Signed-off-by: Giancarlo Stasi <giancarlo.stasi.co@gmail.com>
According to RM, when increasing the CPU frequency, the new number of
wait states to the Flash latency bits must be written and verified
before modifying the CPU clock source and/or the CPU clock prescaler,
to prevent NMI to occur; when decreasing the CPU frequency, after.
Tested with STM32L462 SOC and MSI with several frequencies, both
increasing and decreasing. HSE built, not tested.
Signed-off-by: Giancarlo Stasi <giancarlo.stasi@nexxiot.com>
Several shell modules use cloned code to iterate over all devices and
identify the nth instance that meets some criteria. The code was
repetitive and included various errors. Abstract to a helper function
that performs the check consistently.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
RF SPDT switches used for RX/TX selection have often power enable pin
connected to MCU's GPIO, so it is possible to disable it to save power
when not doing any data transfers. Add 'antenna-enable-gpios' property
to support such designs.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Add support for TCXO power control using GPIO pin. Some boards
(including B-L072Z-LRWAN1 already supported in Zephyr) need delay
applied after powering on TCXO, so add device-tree property allowing to
configure that as well. Cache information about TCXO power status, so
subsequent requests to enable it will not result in unnecessary delays.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
There are several antenna path designs on SX1276 compatible boards in
the wild. B-L072Z-LRWAN1 board has dedicated enable pins for RFI, RFO
and PA_BOOST. This is exactly what this patch allows to
configure. Second variant of antenna selection is done with a single
GPIO pin, which controls RF SPDT switches (input or output). This is
also supported, when either 'rfo-enable-gpios' or
'pa-boost-enable-gpios' property is provided alone (RFO/PA_BOOST is
selected only when transmitting, so there is no need for explicit
'rfi-enable-gpios' configuration).
Drop requirement for 'power-amplifier-output' DT property when there is
either 'rfo-enable-gpios' or 'pa-boost-enable-gpios' configured. Fail
using BUILD_ASSERT() when neither is specified.
Make the SX1276SetAntSw() logic similar to loramac-node examples
implementation, so RFO/PA_BOOST is enabled only in
RFLR_OPMODE_TRANSMITTER.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
PA selection mainly depends on board design. So it looks like
device-tree is a better mechanism than Kconfig in this case. Use string
property with two possible values: "rfo" and "pa-boost".
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
All fields in PA_CONFIG register are set explicitly, so there is no need
to read this register first.
Suggested-by: Andreas Sandberg <andreas@sandberg.pp.se>
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
The PA_CONFIG register is currently not setup correctly for the RFO
path. The biggest problem is that the output power is incorrectly set
1dBm higher than requested. Additionally, the lower power levels are
not configured properly since the max power field in PA_CONFIG is
always configured for an output power between 0 and 15dBm.
To support lower than 0dBm, adjust the max power field in the
PA_CONFIG register to shift the output power range to -4--11 dBm when
the requested power is 0 or lower.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[Marcin: rebase on master]
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Some flash controllers support operations only when buffers are word
aligned. An example of such is nRF QSPI, which checks input buffer using
nrfx_is_word_aligned() function inside nrfx_qspi_write().
Align test array on 4 bytes, so we will gain compatibility with more
flash controllers, including nRF QSPI.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
With addition of flash_parameters structure, and supporting API call
to retrieve it, it is no longer needed to store write_block_size as
a part of flash_driver_api and it should be part of flash_parameters.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
With addition of flash_get_parameters API call, it is needed to provide
support for the API to flash drivers.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Add support to register callback function for each PCIe reset.
These callback functions are executed from corresponding
PCIe reset interrupt handler if registered.
Signed-off-by: Shivaraj Shetty <shivaraj.shetty@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add reset interrupt handlers for all three types of reset
interrupts that iProc PCIe EP can receive - namely PERST,
INB PERST and FLR.
Signed-off-by: Shivaraj Shetty <shivaraj.shetty@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add support for the polarity flag in the STM32 PWM driver.
STM32 boards using PWM have been updated accordingly.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The PWM drivers has been refactored using the HAL LL API. Not only that,
but the set pin_set function is now faster, as channel output compare is
just initialized if needed.
NOTE: Has been tested using H743zi board for now.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a DSB before doing WFE in get_entropy_isr, to ensure
the memory transactions are complete.
Add a note clarifying a dependency for the existing solution
(dependency is satisfied by ARCH code but is good to state
clearly).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We need to clear the NVIC Pending bit for the RNG IRQ before
doing any WFEs and expect to wake up by RNG events. This is
because the event register will be set only if NVIC status
is changed from 0 to 1.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Appropriate WS can be loaded automatically if
the display controller has integrated temperature
sensor or an external sensor is connected.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Fixes the bq274xx sensor driver to check the i2c device pointer is
non-null, rather than the bq274xx sensor device pointer. This appears to
be the originally intended check based on the LOG_ERR message.
Coverity CID: 210035
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Initialize the dummy data transfer so spi transfer is defined even for
an undefined tx data buffer. This aligns the rv32m1 spi driver with the
mcux spi driver.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
Aligns MAC registers to the latest reference manual.
Replaces NULL buffers as some SPI drivers will fail.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
The CONFIG_BT_RPMSG_NRF53 should depend on the SOC, not the BOARD
definition. Otherwise this will break for custom boards.
Signed-off-by: Thomas Stenersen <thomas.stenersen@nordicsemi.no>
