mtls_session_setup checks early if the given mode is valid and return
an error if not. CRYPTO_CIPHER_MODE_CTR is not a valid one so there is
no needed to have it in the switch.
CID: 20600
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The `irq_update` UART API function must always return 1 according to
the API documentations.
This commit fixes the `irq_update` API function to unconditionally
return `1`.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The `irq_update` UART API function must always return 1 according to
the API documentations.
This commit fixes the `irq_update` API function to unconditionally
return '1'.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit fixes the multiple SERCOM interrupt handling for the SAM
D5x and E5x devices by replacing the obsolete device tree symbol with
the new `DT_INST` symbol.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Since driver is shared with other devices, it must be enabled
conditionally based on the number of instances. This avoid show
invalid options for devices with lower port count like SAM4S/SAM4E.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
SAMV71 uses same driver of SAME70 and this enables the feature. Since
driver is shared with other devices, it must be enabled conditionally
based on the number of instances. This avoid show invalid options for
devices with lower port count like SAM4S/SAM4E.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
When added SAM4E and SAMV71 platform the huge amount of refactor left
out this two configurations. This add missing configuration for all
supported devices.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Instead of hardcoding the "zeth" network interface name, use the
name defined in Kconfig so that user can change it if needed.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Move auto-negotiate sequence from driver initialization to link up event
Previously when booting without ethernet cable connected the
initialization would fail and never recover.
Now we can connect the ethernet cable any time and multiple times.
This also drastically reduces boot time to main.
Logging Link up and Link down events.
Logging speed and duplex from eth_gecko logger instead of eth_gecko_phy.
Signed-off-by: Luuk Bosma <l.bosma@interay.com>
pin is an unsigned variable so there is no meaning check if it is less
than zero.
CID :208407
CID :208408
CID :208410
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The rx timeout timer callback need update trx_state variable and this
variable is protected by a mutex. Because of that, when compiling the
system with CONFIG_ASSERT=y the system reports 'ASSERTION FAIL
[!arch_is_in_isr()] @ ZEPHYR_BASE/kernel/include/ksched.h:262'.
This refactor the driver remove trx_state variable dependency and
consequently removes phy_mutex and rx timeout timer to be compliant
with kernel rules.
Fixes: #23198
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current version of at86rf2xx RX implementation don't uses advanced
capabilities offer by the transceiver. This access SRAM space to gatter
PHR information in parallel with transceiver frame reception. It allows
improve RX reception by handling properlly the frame protection feature
removing transceiver states changes.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Current rf2xx_thread_main code have too many if/for/while imbrication.
Extract methods from rx2xx_thread_main for better readability.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Do not use the content of the status register to write into the
override register because it may have unpredictable effect,
instead to a read/modify/write on the override register.
Signed-off-by: Armand Ciejak <armandciejak@users.noreply.github.com>
It is necessary to poll the ENET_EIR_MII bit before reading
the data register as explained in the i.MX RT1060 reference
manual in chapter 41.7.17.4.
Use PHY_* functions from NXP HAL to correctly access the PHY
registers.
Signed-off-by: Armand Ciejak <armandciejak@users.noreply.github.com>
This enables the ADC output data to be shifted right when using
10-bit resolution. Or else, data would be left justified as if
it's doing 12-bit ADC with the right 2 bits filled with zeroes.
Fixes#23202
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit fixes the multiple SERCOM interrupt handling for the SAM
D5x and E5x devices by replacing the obsolete device tree symbol with
the new `DT_INST` symbol.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Improve priority queue conditional build. Now priority queue code is
enabled only if device have support to it. This enables GMAC driver
for devices with only one queue for RX/TX.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The Atmel SAM SoC with ethernet port uses same GMAC driver. However,
there are differences between SoC GMAC implementation. Some SoCs have
priority queue and system can configure 0 up to 5, depending of SoC
version. This update current GMAC driver adding missing definitions.
Co-authored-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add missing queue entries for sam gmac. This update the queue selection
to proper handle all supported SAM SoC that uses GMAC driver.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The first revision of the SAM E70 soc had three queues. The current
revision B has six queues. If we don't initialize all queues, the DMA
engine gets stuck when trying to read a descriptor from NULL. To enable
the initialization of the additional queues, the correct soc has to be
selected in the config options, f.ex. CONFIG_SOC_PART_NUMBER_SAME70Q21B
instead of CONFIG_SOC_PART_NUMBER_SAME70Q21.
Also rename GMAC_QUEUE_NO to GMAC_QUEUE_NUM as requested during review.
Signed-off-by: Daniel Glöckner <dg@emlix.com>
When debugging on a long running platform, the MCU may get reset by
the debugger with an ndmreset toggle. Since there is no requirement
that this resets anything in particular on the platform, the CLINT
registers may not get reset. When this occurs with an mtime register
value that is larger than 32 bits the riscv machine timer will
continuously interrupt the system when the mtime register exceeds 32
bits in value. This is because the last_count value is used to update
the mtimecmp register, and its value is initialized to zero. Its
first update is with a 32-bit value, which loses information when the
mtime register exceeds 32 bits.
The proposed solution is to set the last_count value to the current
value in the mtime register when the timer is initialized. Since the
timer is fired at intervals that are less than 32 bits in value, the
next update of last_count will remain valid, and the system will
function as expected.
Signed-off-by: Jaron Kelleher <jkelleher@fb.com>
This reverts commit 382e6fbccf.
Disabling watchdog at boot breaks watchdog API contract. Production
firmware should never ship with the option enabled. Unfortunately, this
is dangerosly easy to overlook. If left enabled, in the best case, it
will degrade functionality of the subsystem. In the worst case it
will leave watchdog permanently disbled.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
CLOE (Code Loop Optimization) does not exist on SAM3x.
Make the EEFC_FMR_CLOE disable depending on CONFIG_SOC_SERIES_SAM3X.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
Include stm32XXxx_ll_utils.h in soc.h for every stm32 SoC,
if CONFIG_HWINFO_STM32 is selected.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
Make the NRF hwinfo driver depending on !TRUSTED_EXECUTION_NONSECURE
because the FICR registers are not accessible from the non-secure
world.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
Introduce the HWINFO_HAS_DRIVER Kconfig symbol to get
the information if hwinfo is supported on the current platform.
Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
This patch activates the boost mode for the main regulator
when the system frequency above 80MHz for stm32l4Rx/stm32l4Sx
soc series.
To save power, the boost mode should be disabled below 80MHz.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patch activates the boost mode for the main regulator
when the system frequency above 150MHz for stm32g4xx soc series.
To save power, the boost mode should be disabled below 150MHz.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patches add a delay after setting the watchdog
to wait for the register (Prescaler and Counter registers)
to be updated before leaving (until LL_IWDG_IsReady is true)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
SMI initialization is required to enable PHY communication.
PHY setups needs to run after SMI initialization.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
The LIS3MDL sensor provides two different pins for handling
interrupts: the DRDY, that triggers new data sample availability,
and INT, that goes off when data sample exceeds a given threshold.
The driver handled data ready triggers only, which does not
require sensor configuration at all. Moreover a dummy read is
required when the data ready is configured to re-trigger a new
interrupt.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
If IO APIC is in logical destination mode, local APICs compare their
logical APIC ID defined in LDR (Logical Destination Register) with
the destination code sent with the interrupt to determine whether or not
to accept the incoming interrupt.
This patch programs LDR in xAPIC mode to support IO APIC logical mode.
The local APIC ID from local APIC ID register can't be used as the
'logical APIC ID' because LAPIC ID may not be consecutive numbers hence
it makes it impossible for LDR to encode 8 IDs within 8 bits.
This patch chooses 0 for BSP, and for APs, cpu_number which is the index
to x86_cpuboot[], which ultimately assigned in z_smp_init[].
Signed-off-by: Zide Chen <zide.chen@intel.com>
Currently IO APIC is working in physical destination mode, which
doesn't support interrupt to be delivered to multiple local APICs.
By definition only 4 bits [59:63] in IO APIC IOREDTBL register are
available for destination addresses and it contains an APIC ID only.
This patch changes it to logical destination mode so that IOREDTBL
can potentially define a set of processors and it's posible to deliver
interrupts to multiple APICs.
Also it changes delivery mode from fixed to lowest priority. The reason
being in fixed mode, the interrupt could be delivered to all CPUs
which put burden in software to handle repeated interrupts. While in
lowest priority mode, interrupt is delivered to one local APIC only.
Signed-off-by: Zide Chen <zide.chen@intel.com>
During driver rewrite, the field to specify the base address of
the interrupt controller was dropped, which results in error in
device initialization due to accessing random address (or null).
Fix it by specifying the base address.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
On stm32f302/3 series, USB and CAN_1 share same IRQ lines.
To use USB and CAN_1 together, USB IRQ could be remap to other
line numbers, on which there is no conflict.
Remap the USB IRQ lines by default:
-Assign remap number in matching dtsi files
-Perform remap before usb driver init
Additionally, fix compilation issue in usb driver.
Fixes#22343
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Disabling gpio interrupts on the pin prior to changing its interrupt
type to level-based helps prevent spurious interrupts that would be
otherwise observed, if gpio interrupts were originally enabled when
gpio_cc32xx_pin_interrupt_configure() is invoked.
Fixes#22847
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
In the gpio isr, gpio interrupts are disabled when invoking the
registered callbacks. This is unnecessary, and causes a problem if the
callback attempts to disable gpio interrupts by reconfiguring the pin
as in the test gpio_basic_api.
Fixes#22847
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Include gpio_utils.h to fix a build failure:
gpio_pca95xx.c:490:20: warning: implicit declaration of
function 'GPIO_PORT_PIN_MASK_FROM_NGPIOS'
[-Wimplicit-function-declaration]
gpio_pca95xx.c:490:20: error: initializer element is not constant
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(
DT_INST_##inst##_NXP_PCA95XX_NGPIOS), \
Signed-off-by: Göran Weinholt <goran.weinholt@endian.se>
