Commit graph

6 commits

Author SHA1 Message Date
Kumar Gala a1b77fd589 zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-06-08 08:23:57 -05:00
Tomasz Bursztyka 97326c0445 device: Fix structure attributes access
Since struct devconfig was merged earlier into struct device, let's fix
accessing config_info, name, ... attributes everywhere via:

grep -rlZ 'dev->config->' | xargs -0 sed -i 's/dev->config->/dev->/g'

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-05-08 23:07:44 +02:00
Song Qiang f0d3ee52fb drivers: i2s: change the stm32 DMA in the driver to use dts
This commit moves DMA parameters previously hard coded in the driver
to the dts.

Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-11-06 14:14:39 +01:00
Song Qiang 9561785ea7 drivers: i2s: add some missing DMA parameters
src_addr_increment, dst_addr_increment, fifo_threshold and priority
are missing as parameters for configuring DMA. This commit adds them
to the driver.

Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
2019-11-06 14:14:39 +01:00
Song Qiang ad5f81b2e7 drivers: i2s: change stm32 i2s driver to use two DMA controllers
The i2s driver assumes the tx channel and rx channel of dma are using
the same dma controller. This commit changes it to be able to use
different dma controllers.

Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
2019-11-06 14:14:39 +01:00
Armando Visconti 7b82e9f2d0 drivers: i2s: Add support for I2S stm32
STM32 I2S driver implementation. It has been designed in the most
generic way possible, with the possibility of using it in master/slave
and rx/tx mode. Currenty it has been tested for master rx mode only
using the microphone on ArgonKey board.

The configuration file permits to compile it for STM32F4xx product
family only, but it should be easy to extend it also for other
families.

It supports all 5 STM32F4xx I2S controllers (I2S 1/4/5 on APB2 and
I2S 2/3 on APB1).
It makes uses of the available DMA channels for rx/tx streams.

The clock source can be selected among one of the following two choices:

  - PLLI2S pll, with possibility to configure PLLM/PLLN/PLLR
  - HSE/HSI clock

Interrupt is triggered only in case of errors (FRM/OVR/UDR).

Signed-off-by: Armando Visconti <armando.visconti@st.com>
2018-10-11 16:55:00 +02:00