Replace individual device instance definitions with the macro that
expands to the equivalent change.
F='struct device DEVICE_NAME_GET'
git grep -l "$F" \
| xargs sed -i -r \
-e "s@$F"'\(([^)]*)\);@DEVICE_DECLARE(\1);@'
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Move from a Kconfig to select/initialize the MAC address to using the
"local-mac-address" property in devicetree. If the property is set the
drivers will initialize the mac-address from the devicetree (unless the
mac address is all 0's). The MAC address might get overwritten by
either a driver specific means or by the setting of
"zephyr,random-mac-address" in the devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Utilize the devicetree property "zephyr,random-mac-address" to determine
if a driver should use a random mac address and remove the associated
Kconfig options that enabled this feature.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rather than having each driver have its own slightly different way of
generating a random mac address, add a helper function that they all can
call so we do it one way.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Reworked sam_gmac driver to get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h
We remove defines from soc_pinmap.h that are no longer needed due to
getting all that information from devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds the GMAC driver support for the Ethernet-capable SAM0
family devices (SAM E53 and E54 at this time).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit updates the Atmel SAM GMAC driver to select max frame size
value from the device tree. Now GMAC driver can operate with the three
different frame size options available.
The current supported values are: 1518, 1536 and 10240.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current setup of physical layer forces RMII interface. The code was
refactored to have only one point to select proper phy interface. Now,
GMAC driver works with both RMII or MII interface. The phy connection
type is now selected by device tree. The default phy connection is RMII.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Improve data cache conditional build. Now data cache code is build
only if device have support to it. This enables GMAC driver for use
with devices that don't have data cache instructions.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This cleans up DMA flags by separating the necessary flags for devices
with one or multiple RX/TX queues.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit updates the Atmel SAM GMAC driver to use the device tree
values for GMAC hardware configuration.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
By changing the various *NET_DEVICE* macros. It is up to the device
drivers to either set a proper PM function or, if not supported or PM
disabled, to use device_pm_control_nop relevantly.
All existing macro calls are updated. Since no PM support was added so
far, device_pm_control_nop is used as the default everywhere.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The Atmel DFP headers define two "component typedef styles": RFO and
NTO; where the latter makes use of bit field structs to access hardware
registers.
The default component typedef style assumed by the DFP headers (i.e.
when `COMPONENT_TYPEDEF_STYLE` is not explicitly defined) is "RFO" and
this is indeed the component typedef style used throughout the Zephyr
Atmel SAM drivers, except in the particular instance which this commit
addresses.
The use of `GMAC_TA_Type` bit field struct, which is an "NTO" style
construct, is no longer possible with the latest DFPs because
conditional compilation checks for the bit field struct definitions
were added to restrict the use of such constructs to only when the
global component typedef style is set to "NTO".
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds the "monitor task" to detect and report any changes
in the PHY link status to the operating system.
The monitor task is perodically executed to poll the link status from
the PHY and call `net_eth_carrier_{off,on}` based on the detected
link status change.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The `link_configure` function currently configures the `GMAC_UR`
register and forces the RMII interface.
This is not necessary because the `GMAC_UR` register is already
configured with an appropriate value based on `CONFIG_ETH_SAM_GMAC_MII`
in `gmac_init`.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Improve priority queue conditional build. Now priority queue code is
enabled only if device have support to it. This enables GMAC driver
for devices with only one queue for RX/TX.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The Atmel SAM SoC with ethernet port uses same GMAC driver. However,
there are differences between SoC GMAC implementation. Some SoCs have
priority queue and system can configure 0 up to 5, depending of SoC
version. This update current GMAC driver adding missing definitions.
Co-authored-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The first revision of the SAM E70 soc had three queues. The current
revision B has six queues. If we don't initialize all queues, the DMA
engine gets stuck when trying to read a descriptor from NULL. To enable
the initialization of the additional queues, the correct soc has to be
selected in the config options, f.ex. CONFIG_SOC_PART_NUMBER_SAME70Q21B
instead of CONFIG_SOC_PART_NUMBER_SAME70Q21.
Also rename GMAC_QUEUE_NO to GMAC_QUEUE_NUM as requested during review.
Signed-off-by: Daniel Glöckner <dg@emlix.com>
If the Ethernet driver has VLAN enabled (only native_posix, mcux
or gmac has VLAN supported), then the iface pointer in ethernet
context should contain the main network interface. This is needed
so that the interface will get link address set to it properly.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
When randomly generating MAC addresses they will always be
locally administrated addresses, so the LAA bit should be set.
The LAA bit is the 2nd bit of the 1st byte of the MAC address
not the 2nd bit of the 4th byte.
Fixes: #16452
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move misc/__assert.h to sys/__assert.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move i2c.h to drivers/i2c.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some places were still using the old allocator. Using the new one does
not change any behavior. This will help to remove the useless data_len
attribute in net_pkt which legacy allocator was still setting.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Removing the TX timeout handling in the GMAC driver (commit 18b07e09e0)
revealed some issues with the way hardware priority queues work.
For cases with both hardware priority queues enabled, with the default
recommended delta bandwidths (0% - 75%), the lower priority queue (0%)
is hardly able to send any packets. This became visible, because without
the timeout mechanism, we quickly ran out of available TX buffers if
there were multiple packets being queued to the queue.
Here is an excerpt from 802.1Q, chapter 34.3.1 which describes how Qav
bandwidth sharing SHOULD work:
The deltaBandwidth(N) for a given N, plus the deltaBandwidth(N) values
for any higher priority queues (larger values of N) defines the total
percentage of the Port’s bandwidth that can be reserved for that queue
and all higher priority queues. For the highest priority queue, this
means that the maximum value of operIdleSlope(N) is deltaBandwidth(N)%
of portTransmitRate. However, if operIdleSlope(N) is actually less
than this maximum value, any lower priority queue that supports the
credit-based shaper algorithm can make use of the reservable bandwidth
that is unused by the higher priority queue. So, for queue N-1, the
maximum value of (operIdleSlope(N) + operIdleSlope(N-1)) is
(deltaBandwidth(N) + deltaBandwidth(N1))% of portTransmitRate.
However in reality, the lower priority queues (N-1) on the SAM GMAC
hardware DO NOT use the bandwidth available from the higher priority
queues (N).
This commits fixes the issue by changing the defaults. These are still
set to the recommended 75% (total), but this percentage is split between
the priority queues manually.
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
There is a log message printed for the non-priority queue (Queue 0). Add
the same message for the priority queues too when they are enabled, and
a corresponding message when the queue is not used (set to idle).
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Throughout the manual, the queues GMAC is equipped with are identified
by a number - Queue 0, Queue 1 and Queue 2.
However in the context of Qav, the queues are identified with a
character (note that there are only two queues as Qav is not used for
the non-priority queue) - Queue A and Queue B.
Queue B and Queue 2 are also called "the highest priority queues".
Based on that, the previous implementation was using the following
mapping:
Queue 1 - Queue A
Queue 2 - Queue B
However when running some specific tests, that is for example forcing
all the traffic to Queue 1, it showed that this queue is actually
affected by the Queue B registers. Similarly, Queue 2 seems to be
affected by the Queue A registers.
Based on that observation, this commit changes the registers used to
work with the following mapping:
Queue 1 - Queue B
Queue 2 - Queue A
Note that this is based solely on observations, there is nothing in the
datasheet that confirms this, and the "highest priority" label suggests
it is otherwise.
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
This option is meant to be used only for debugging. Use it to force all
traffic to be routed through a specific hardware queue. With this option
enabled it is easier to verify whether the chosen hardware queue
actually works.
This works only if there are four or fewer RX traffic classes enabled as
the SAM GMAC hardware supports screening up to four traffic classes.
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
The j iterator is used for priorities, and the i iterator is used for
choosing the actual screening register. Therefore the screening register
availability needs to be checked with i.
This commit also improves the readability by doing two things:
* by moving the screening register index check to a place where the
index is going to be actually used
* by using the ARRAY_SIZE macro instead of a hard-coded number as the
upper limit
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
The ring_buf implementation is basically used as an array of net_buf
pointers in the RX path. The tail and head indexes are taken from the
RX descriptors and not from the ring_buf. That's why for example the
fact that head is never initialized doesn't cause problem. Only len is
used in free_rx_bufs(), but anyway this function is plainly broken as
it always free the first net_buf and doesn't set it back to NULL.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Scale down the TX path of the GMAC driver by waiting for a packet to be
fully sent before returning from the send function. This has a small
performance impact, but has a few advantages:
- It allows the Ethernet code to modify the packet afterward, fixing PTP
support on this board (see PR #12563).
- It returns an error to the IP stack in case of a transmit failure.
- It doesn't require net_buf to be thread safe.
This change can be reverted by changing GMAC_MULTIPLE_TX_PACKETS from 0
to 1.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The GMAC driver tries to ensure that it can always send a complete
Ethernet frame. However in the TX path this is the problem of the IP
stack: if the buffers can't be allocated, they won't be sent. Therefore
just drop the check.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The SAM GMAC Ethernet driver currently keeps a reference to the packet
being sent in addition than keeping of references of the fragments. In
practice this is only needed when PTP is enabled, otherwise the driver
only need to prevent the fragment (or even their content) to be changed.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The SAM GMAC Ethernet driver uses scatter gather DMA to transmit data.
Each fragment of a network packet is mapped from a set of descriptors
that is used by the controller to do the DMA transfer. This means that
the packet is not necessary sent when the send() function returns. For
that reason the driver calls net_pkt_ref() on the packet to prevent it
from being freed. It is then unreferenced with net_pkt_unref() in the
TX ISR when the packet has effectively been sent.
However this doesn't work if the packet is modified in the meantime,
like it will be done in PR #12563 to remove the Ethernet header
contained in the first fragment. To avoid that, call net_pkt_frag_ref()
on each fragment of the packet, and unreferenced them with
net_pkt_frag_unref() in the TX ISR when the packet has effectively been
sent.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Replace the sole use of i2c_burst_read_addr with a more generic API
function to allow the former to be deprecated along with its unreliable
sibling write and update functions.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Previous SAM E70 HAL version was patched by commit 4dcfc8706 ("Add
missing interrupt number definitions") to add missing interrupt
definitions for SAM GMAC Priority Queues. This has been fixed in the
latest HAL by using a slightly different name. This patch updates the
driver accordingly.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Now that the descriptor lists are in non-cached memory, the helpers are
just accessing the w0 or w1 members of the structure. Just drop them and
access the members directly.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Atmel SAM Ethernet module is using a scatter-gather technique to
exchange data with the Ethernet driver. To communicate the location
of the data buffers the driver sets-up a so called descriptor list. This
is effectively a place in RAM containing a sequence of 32-bit words
representing buffer location and its status.
Currently the cache coherency is handled using cache clean or
invalidate. Unfortunately this strategy only works correctly when the
corresponding data size is a multiple of the cache line. This is not
the case here and might lead to data loss or corruption.
Instead of using cache operations, this patch moves the descriptor
listed to the recently added non-cached memory region, as recommended by
ATMEL. A data synchronisation barrier is still required for writes, as
the non-cached memory is defined with TEX=1, i.e. it is not strongly
ordered. The descriptor lists alignment can be decreased to 4 bytes, as
required by the SAM Ethernet module.
The RX/TX buffer are left unchanged, still managed by cache operations.
Fixes#9812
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The RX buffer accounting list is not a list shared with Ethernet device,
therefore there is no need to run a cache clean operation on it.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The SAM E70 GMAC ethernet driver reference a packet with net_pkt_ref()
when queueing a packet, and unreference it with net_pkt_unref() in the
ISR when it has been fully sent.
The call to net_pkt_ref() is done just after re-enabling the
interruptions, so there is however a small race condition that might
cause the packet to be unreference before being referenced. This is
only theoretical and has not been seen in practice.
Fix that by moving the call to net_pkt_ref() just before re-enabling
the interruptions.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The SAM E70 Ethernet driver uses scatter gather DMA to transmit data.
Each fragment of a network packet is mapped from a set of descriptors
that is used by the controller to do the DMA transfer. Each descriptor
contain an address and a length/status. The important status bits are
GMAC_TXW1_LASTBUFFER to indicate the last fragment of a packet and
GMAC_TXW1_USED to indicate that a descriptor has been processed by the
controller.
When starting a transmission, the controller start at the descriptor
after the last one that has been processed. If the descriptor is NOT
flagged by GMAC_TXW1_USED, it sends a first packet by sending all the
fragments up to a descriptor flagged with GMAC_TXW1_LASTBUFFER. The
first descriptor of a packet *and only the first descriptor of a packet*
is then modified to flag it with GMAC_TXW1_USED and to provide a status
(mostly related to errors and checksum offloading). It then continues
with the next packet and so on and only stops if the next descriptor
after GMAC_TXW1_LASTBUFFER is flagged with GMAC_TXW1_USED.
Therefore in order for the controller to stop processing descriptors,
the strategy is to flag the next descriptor after the last fragment to
be sent with GMAC_TXW1_USED. When the next packet has to be queued, the
flag can be removed before starting a transmission.
This is what is currently done in the current driver. However there is a
small race condition in the implementation: if packets are queued fast
enough, the controller is still sending the fragment of the previous
packet when the descriptor are written. When writing the first
descriptor, the GMAC_TXW1_USED flag is removed. This is done after
writing the address (with a memory barrier) so that looks safe. However
given that the GMAC_TXW1_USED flag is only added by the controller to
the first descriptor of a packet it means the next descriptor might
have it cleared. In that case the descriptor is processed, and a junk
packet is sent. That also desynchronize eth_tx and tx_complete as one
or more packets than expected are transmitted.
In order to fix that the strategy is slightly changed to initially write
the first descriptor with the GMAC_TXW1_USED flag set. Once all the
descriptors from the packet are written the bit is cleared (after a
memory barrier). Then the transmission can be started safely.
The patch also does a small optimization writing the next descriptor
with only the GMAC_TXW1_USED bit set instead of setting this bit. As
this will be a non-cached area, it's better avoiding a read followed
by a write if not necessary.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The current SAM E70 Ethernet driver sometimes get stuck if the stack
has to send 2 packets in a row, for example an ack for the just received
data + answer data.
The problem is the following one:
1) The first packet goes through eth_tx, one tx_desc_sem semaphore is
taken, and the tx_timeout_work delayed work is submitted.
2) The second packet also goes through eth_tx, another tx_desc_sem
semaphore is taken, and the tx_timeout_work delayed work is not
started because there is already one already submitted.
3) The first packet has been sent, one tx_desc_sem semaphore is given
and the tx_timeout_work delayed work is cancelled.
4) The second packet has been sent but given the delayed work has
already been cancelled, tx_completed is not called: the tx_desc_sem
semaphore is not given back and the network packet is not
unreferenced.
The whole timeout concept probably has to be reworked. In the meantime
it is probably better to just drop the timeout code instead of keeping
the driver broken. We can only get stuck on the TX path if there is a
bug in the driver or a hardware malfunction. It might happen, but with
the less probability then the current hangs. In addition it just hides
the real issues and prevent them to be fixed.
This commit therefore just remove the timeout code in the TX path.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
