drivers: ethernet: eth_sam_gmac: Add SAM0 family support
This commit adds the GMAC driver support for the Ethernet-capable SAM0 family devices (SAM E53 and E54 at this time). Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis
Kumar Gala
parent
a399c90009
commit
5b248ce792
3 changed files with 162 additions and 2 deletions
134
drivers/ethernet/eth_sam0_gmac.h
Normal file
134
drivers/ethernet/eth_sam0_gmac.h
Normal file
|
|
@ -0,0 +1,134 @@
|
|||
/*
|
||||
* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_SAM0_GMAC_H_
|
||||
#define ZEPHYR_DRIVERS_ETHERNET_ETH_SAM0_GMAC_H_
|
||||
|
||||
/*
|
||||
* Map the SAM-family DFP GMAC register names to the SAM0-family DFP GMAC
|
||||
* register names.
|
||||
*/
|
||||
#define GMAC_NCR NCR.reg
|
||||
#define GMAC_NCFGR NCFGR.reg
|
||||
#define GMAC_NSR NSR.reg
|
||||
#define GMAC_UR UR.reg
|
||||
#define GMAC_DCFGR DCFGR.reg
|
||||
#define GMAC_TSR TSR.reg
|
||||
#define GMAC_RBQB RBQB.reg
|
||||
#define GMAC_TBQB TBQB.reg
|
||||
#define GMAC_RSR RSR.reg
|
||||
#define GMAC_ISR ISR.reg
|
||||
#define GMAC_IER IER.reg
|
||||
#define GMAC_IDR IDR.reg
|
||||
#define GMAC_IMR IMR.reg
|
||||
#define GMAC_MAN MAN.reg
|
||||
#define GMAC_RPQ RPQ.reg
|
||||
#define GMAC_TPQ TPQ.reg
|
||||
#define GMAC_TPSF TPSF.reg
|
||||
#define GMAC_RPSF RPSF.reg
|
||||
#define GMAC_RJFML RJFML.reg
|
||||
#define GMAC_HRB HRB.reg
|
||||
#define GMAC_HRT HRT.reg
|
||||
#define GMAC_SA Sa
|
||||
#define GMAC_WOL WOL.reg
|
||||
#define GMAC_IPGS IPGS.reg
|
||||
#define GMAC_SVLAN SVLAN.reg
|
||||
#define GMAC_TPFCP TPFCP.reg
|
||||
#define GMAC_SAMB1 SAMB1.reg
|
||||
#define GMAC_SAMT1 SAMT1.reg
|
||||
#define GMAC_NSC NSC.reg
|
||||
#define GMAC_SCL SCL.reg
|
||||
#define GMAC_SCH SCH.reg
|
||||
#define GMAC_EFTSH EFTSH.reg
|
||||
#define GMAC_EFRSH EFRSH.reg
|
||||
#define GMAC_PEFTSH PEFTSH.reg
|
||||
#define GMAC_PEFRSH PEFRSH.reg
|
||||
#define GMAC_OTLO OTLO.reg
|
||||
#define GMAC_OTHI OTHI.reg
|
||||
#define GMAC_FT FT.reg
|
||||
#define GMAC_BCFT BCFT.reg
|
||||
#define GMAC_MFT MFT.reg
|
||||
#define GMAC_PFT PFT.reg
|
||||
#define GMAC_BFT64 BFT64.reg
|
||||
#define GMAC_TBFT127 TBFT127.reg
|
||||
#define GMAC_TBFT255 TBFT255.reg
|
||||
#define GMAC_TBFT511 TBFT511.reg
|
||||
#define GMAC_TBFT1023 TBFT1023.reg
|
||||
#define GMAC_TBFT1518 TBFT1518.reg
|
||||
#define GMAC_GTBFT1518 GTBFT1518.reg
|
||||
#define GMAC_TUR TUR.reg
|
||||
#define GMAC_SCF SCF.reg
|
||||
#define GMAC_MCF MCF.reg
|
||||
#define GMAC_EC EC.reg
|
||||
#define GMAC_LC LC.reg
|
||||
#define GMAC_DTF DTF.reg
|
||||
#define GMAC_CSE CSE.reg
|
||||
#define GMAC_ORLO ORLO.reg
|
||||
#define GMAC_ORHI ORHI.reg
|
||||
#define GMAC_FR FR.reg
|
||||
#define GMAC_BCFR BCFR.reg
|
||||
#define GMAC_MFR MFR.reg
|
||||
#define GMAC_PFR PFR.reg
|
||||
#define GMAC_BFR64 BFR64.reg
|
||||
#define GMAC_TBFR127 TBFR127.reg
|
||||
#define GMAC_TBFR255 TBFR255.reg
|
||||
#define GMAC_TBFR511 TBFR511.reg
|
||||
#define GMAC_TBFR1023 TBFR1023.reg
|
||||
#define GMAC_TBFR1518 TBFR1518.reg
|
||||
#define GMAC_TMXBFR TMXBFR.reg
|
||||
#define GMAC_UFR UFR.reg
|
||||
#define GMAC_OFR OFR.reg
|
||||
#define GMAC_JR JR.reg
|
||||
#define GMAC_FCSE FCSE.reg
|
||||
#define GMAC_LFFE LFFE.reg
|
||||
#define GMAC_RSE RSE.reg
|
||||
#define GMAC_AE AE.reg
|
||||
#define GMAC_RRE RRE.reg
|
||||
#define GMAC_ROE ROE.reg
|
||||
#define GMAC_IHCE IHCE.reg
|
||||
#define GMAC_TCE TCE.reg
|
||||
#define GMAC_UCE UCE.reg
|
||||
#define GMAC_TISUBN TISUBN.reg
|
||||
#define GMAC_TSH TSH.reg
|
||||
#define GMAC_TSSSL TSSSL.reg
|
||||
#define GMAC_TSSN TSSN.reg
|
||||
#define GMAC_TSL TSL.reg
|
||||
#define GMAC_TN TN.reg
|
||||
#define GMAC_TA TA.reg
|
||||
#define GMAC_TI TI.reg
|
||||
#define GMAC_EFTSL EFTSL.reg
|
||||
#define GMAC_EFTN EFTN.reg
|
||||
#define GMAC_EFRSL EFRSL.reg
|
||||
#define GMAC_EFRN EFRN.reg
|
||||
#define GMAC_PEFTSL PEFTSL.reg
|
||||
#define GMAC_PEFTN PEFTN.reg
|
||||
#define GMAC_PEFRSL PEFRSL.reg
|
||||
#define GMAC_PEFRN PEFRN.reg
|
||||
#define GMAC_RLPITR RLPITR.reg
|
||||
#define GMAC_RLPITI RLPITI.reg
|
||||
#define GMAC_TLPITR TLPITR.reg
|
||||
#define GMAC_TLPITI TLPITI.reg
|
||||
|
||||
#define GMAC_SAB SAB.reg
|
||||
#define GMAC_SAT SAT.reg
|
||||
|
||||
/*
|
||||
* Define the register field value symbols that are missing in the SAM0-family
|
||||
* DFP GMAC headers.
|
||||
*/
|
||||
#define GMAC_NCFGR_CLK_MCK_8 GMAC_NCFGR_CLK(0)
|
||||
#define GMAC_NCFGR_CLK_MCK_16 GMAC_NCFGR_CLK(1)
|
||||
#define GMAC_NCFGR_CLK_MCK_32 GMAC_NCFGR_CLK(2)
|
||||
#define GMAC_NCFGR_CLK_MCK_48 GMAC_NCFGR_CLK(3)
|
||||
#define GMAC_NCFGR_CLK_MCK_64 GMAC_NCFGR_CLK(4)
|
||||
#define GMAC_NCFGR_CLK_MCK_96 GMAC_NCFGR_CLK(5)
|
||||
|
||||
#define GMAC_DCFGR_FBLDO_SINGLE GMAC_DCFGR_FBLDO(1)
|
||||
#define GMAC_DCFGR_FBLDO_INCR4 GMAC_DCFGR_FBLDO(2)
|
||||
#define GMAC_DCFGR_FBLDO_INCR8 GMAC_DCFGR_FBLDO(3)
|
||||
#define GMAC_DCFGR_FBLDO_INCR16 GMAC_DCFGR_FBLDO(4)
|
||||
|
||||
#endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_SAM0_GMAC_H_ */
|
||||
|
|
@ -41,6 +41,10 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
|
|||
#include "phy_sam_gmac.h"
|
||||
#include "eth_sam_gmac_priv.h"
|
||||
|
||||
#ifdef CONFIG_SOC_FAMILY_SAM0
|
||||
#include "eth_sam0_gmac.h"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PTP_CLOCK_SAM_GMAC)
|
||||
#include <ptp_clock.h>
|
||||
#include <net/gptp.h>
|
||||
|
|
@ -84,6 +88,14 @@ static inline void dcache_clean(u32_t addr, u32_t size)
|
|||
#define dcache_clean(addr, size)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_FAMILY_SAM0
|
||||
#define MCK_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
|
||||
#elif CONFIG_SOC_FAMILY_SAM
|
||||
#define MCK_FREQ_HZ SOC_ATMEL_SAM_MCK_FREQ_HZ
|
||||
#else
|
||||
#error Unsupported SoC family
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Verify Kconfig configuration
|
||||
*/
|
||||
|
|
@ -1037,7 +1049,7 @@ static void gmac_setup_ptp_clock_divisors(Gmac *gmac)
|
|||
|
||||
u8_t cns, acns, nit;
|
||||
|
||||
min_cycles = SOC_ATMEL_SAM_MCK_FREQ_HZ;
|
||||
min_cycles = MCK_FREQ_HZ;
|
||||
min_period = NSEC_PER_SEC;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mck_divs); ++i) {
|
||||
|
|
@ -1069,7 +1081,7 @@ static int gmac_init(Gmac *gmac, u32_t gmac_ncfgr_val)
|
|||
{
|
||||
int mck_divisor;
|
||||
|
||||
mck_divisor = get_mck_clock_divisor(SOC_ATMEL_SAM_MCK_FREQ_HZ);
|
||||
mck_divisor = get_mck_clock_divisor(MCK_FREQ_HZ);
|
||||
if (mck_divisor < 0) {
|
||||
return mck_divisor;
|
||||
}
|
||||
|
|
@ -1752,11 +1764,17 @@ static int eth_initialize(struct device *dev)
|
|||
|
||||
cfg->config_func();
|
||||
|
||||
#ifdef CONFIG_SOC_FAMILY_SAM
|
||||
/* Enable GMAC module's clock */
|
||||
soc_pmc_peripheral_enable(cfg->periph_id);
|
||||
|
||||
/* Connect pins to the peripheral */
|
||||
soc_gpio_list_configure(cfg->pin_list, cfg->pin_list_size);
|
||||
#else
|
||||
/* Enable MCLK clock on GMAC */
|
||||
MCLK->AHBMASK.reg |= MCLK_AHBMASK_GMAC;
|
||||
*MCLK_GMAC |= MCLK_GMAC_MASK;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -2182,13 +2200,17 @@ static void eth0_irq_config(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_FAMILY_SAM
|
||||
static const struct soc_gpio_pin pins_eth0[] = PINS_GMAC0;
|
||||
#endif
|
||||
|
||||
static const struct eth_sam_dev_cfg eth0_config = {
|
||||
.regs = GMAC,
|
||||
.periph_id = ID_GMAC,
|
||||
#ifdef CONFIG_SOC_FAMILY_SAM
|
||||
.pin_list = pins_eth0,
|
||||
.pin_list_size = ARRAY_SIZE(pins_eth0),
|
||||
#endif
|
||||
.config_func = eth0_irq_config,
|
||||
.phy = {GMAC, CONFIG_ETH_SAM_GMAC_PHY_ADDR},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12,6 +12,10 @@
|
|||
#include <net/mii.h>
|
||||
#include "phy_sam_gmac.h"
|
||||
|
||||
#ifdef CONFIG_SOC_FAMILY_SAM0
|
||||
#include "eth_sam0_gmac.h"
|
||||
#endif
|
||||
|
||||
#define LOG_MODULE_NAME eth_sam_phy
|
||||
#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue