drivers: ethernet: eth_sam_gmac: Add SAM0 family support
This commit adds the GMAC driver support for the Ethernet-capable SAM0 family devices (SAM E53 and E54 at this time). Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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a399c90009
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3 changed files with 162 additions and 2 deletions
134
drivers/ethernet/eth_sam0_gmac.h
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134
drivers/ethernet/eth_sam0_gmac.h
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/*
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* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_SAM0_GMAC_H_
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#define ZEPHYR_DRIVERS_ETHERNET_ETH_SAM0_GMAC_H_
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/*
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* Map the SAM-family DFP GMAC register names to the SAM0-family DFP GMAC
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* register names.
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*/
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#define GMAC_NCR NCR.reg
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#define GMAC_NCFGR NCFGR.reg
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#define GMAC_NSR NSR.reg
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#define GMAC_UR UR.reg
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#define GMAC_DCFGR DCFGR.reg
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#define GMAC_TSR TSR.reg
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#define GMAC_RBQB RBQB.reg
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#define GMAC_TBQB TBQB.reg
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#define GMAC_RSR RSR.reg
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#define GMAC_ISR ISR.reg
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#define GMAC_IER IER.reg
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#define GMAC_IDR IDR.reg
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#define GMAC_IMR IMR.reg
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#define GMAC_MAN MAN.reg
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#define GMAC_RPQ RPQ.reg
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#define GMAC_TPQ TPQ.reg
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#define GMAC_TPSF TPSF.reg
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#define GMAC_RPSF RPSF.reg
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#define GMAC_RJFML RJFML.reg
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#define GMAC_HRB HRB.reg
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#define GMAC_HRT HRT.reg
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#define GMAC_SA Sa
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#define GMAC_WOL WOL.reg
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#define GMAC_IPGS IPGS.reg
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#define GMAC_SVLAN SVLAN.reg
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#define GMAC_TPFCP TPFCP.reg
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#define GMAC_SAMB1 SAMB1.reg
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#define GMAC_SAMT1 SAMT1.reg
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#define GMAC_NSC NSC.reg
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#define GMAC_SCL SCL.reg
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#define GMAC_SCH SCH.reg
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#define GMAC_EFTSH EFTSH.reg
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#define GMAC_EFRSH EFRSH.reg
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#define GMAC_PEFTSH PEFTSH.reg
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#define GMAC_PEFRSH PEFRSH.reg
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#define GMAC_OTLO OTLO.reg
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#define GMAC_OTHI OTHI.reg
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#define GMAC_FT FT.reg
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#define GMAC_BCFT BCFT.reg
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#define GMAC_MFT MFT.reg
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#define GMAC_PFT PFT.reg
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#define GMAC_BFT64 BFT64.reg
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#define GMAC_TBFT127 TBFT127.reg
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#define GMAC_TBFT255 TBFT255.reg
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#define GMAC_TBFT511 TBFT511.reg
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#define GMAC_TBFT1023 TBFT1023.reg
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#define GMAC_TBFT1518 TBFT1518.reg
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#define GMAC_GTBFT1518 GTBFT1518.reg
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#define GMAC_TUR TUR.reg
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#define GMAC_SCF SCF.reg
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#define GMAC_MCF MCF.reg
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#define GMAC_EC EC.reg
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#define GMAC_LC LC.reg
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#define GMAC_DTF DTF.reg
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#define GMAC_CSE CSE.reg
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#define GMAC_ORLO ORLO.reg
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#define GMAC_ORHI ORHI.reg
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#define GMAC_FR FR.reg
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#define GMAC_BCFR BCFR.reg
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#define GMAC_MFR MFR.reg
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#define GMAC_PFR PFR.reg
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#define GMAC_BFR64 BFR64.reg
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#define GMAC_TBFR127 TBFR127.reg
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#define GMAC_TBFR255 TBFR255.reg
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#define GMAC_TBFR511 TBFR511.reg
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#define GMAC_TBFR1023 TBFR1023.reg
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#define GMAC_TBFR1518 TBFR1518.reg
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#define GMAC_TMXBFR TMXBFR.reg
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#define GMAC_UFR UFR.reg
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#define GMAC_OFR OFR.reg
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#define GMAC_JR JR.reg
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#define GMAC_FCSE FCSE.reg
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#define GMAC_LFFE LFFE.reg
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#define GMAC_RSE RSE.reg
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#define GMAC_AE AE.reg
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#define GMAC_RRE RRE.reg
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#define GMAC_ROE ROE.reg
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#define GMAC_IHCE IHCE.reg
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#define GMAC_TCE TCE.reg
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#define GMAC_UCE UCE.reg
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#define GMAC_TISUBN TISUBN.reg
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#define GMAC_TSH TSH.reg
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#define GMAC_TSSSL TSSSL.reg
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#define GMAC_TSSN TSSN.reg
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#define GMAC_TSL TSL.reg
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#define GMAC_TN TN.reg
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#define GMAC_TA TA.reg
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#define GMAC_TI TI.reg
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#define GMAC_EFTSL EFTSL.reg
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#define GMAC_EFTN EFTN.reg
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#define GMAC_EFRSL EFRSL.reg
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#define GMAC_EFRN EFRN.reg
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#define GMAC_PEFTSL PEFTSL.reg
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#define GMAC_PEFTN PEFTN.reg
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#define GMAC_PEFRSL PEFRSL.reg
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#define GMAC_PEFRN PEFRN.reg
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#define GMAC_RLPITR RLPITR.reg
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#define GMAC_RLPITI RLPITI.reg
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#define GMAC_TLPITR TLPITR.reg
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#define GMAC_TLPITI TLPITI.reg
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#define GMAC_SAB SAB.reg
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#define GMAC_SAT SAT.reg
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/*
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* Define the register field value symbols that are missing in the SAM0-family
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* DFP GMAC headers.
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*/
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#define GMAC_NCFGR_CLK_MCK_8 GMAC_NCFGR_CLK(0)
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#define GMAC_NCFGR_CLK_MCK_16 GMAC_NCFGR_CLK(1)
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#define GMAC_NCFGR_CLK_MCK_32 GMAC_NCFGR_CLK(2)
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#define GMAC_NCFGR_CLK_MCK_48 GMAC_NCFGR_CLK(3)
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#define GMAC_NCFGR_CLK_MCK_64 GMAC_NCFGR_CLK(4)
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#define GMAC_NCFGR_CLK_MCK_96 GMAC_NCFGR_CLK(5)
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#define GMAC_DCFGR_FBLDO_SINGLE GMAC_DCFGR_FBLDO(1)
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#define GMAC_DCFGR_FBLDO_INCR4 GMAC_DCFGR_FBLDO(2)
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#define GMAC_DCFGR_FBLDO_INCR8 GMAC_DCFGR_FBLDO(3)
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#define GMAC_DCFGR_FBLDO_INCR16 GMAC_DCFGR_FBLDO(4)
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#endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_SAM0_GMAC_H_ */
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@ -41,6 +41,10 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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#include "phy_sam_gmac.h"
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#include "eth_sam_gmac_priv.h"
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#ifdef CONFIG_SOC_FAMILY_SAM0
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#include "eth_sam0_gmac.h"
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#endif
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#if defined(CONFIG_PTP_CLOCK_SAM_GMAC)
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#include <ptp_clock.h>
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#include <net/gptp.h>
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#define dcache_clean(addr, size)
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#endif
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#ifdef CONFIG_SOC_FAMILY_SAM0
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#define MCK_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#elif CONFIG_SOC_FAMILY_SAM
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#define MCK_FREQ_HZ SOC_ATMEL_SAM_MCK_FREQ_HZ
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#else
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#error Unsupported SoC family
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#endif
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/*
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* Verify Kconfig configuration
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*/
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@ -1037,7 +1049,7 @@ static void gmac_setup_ptp_clock_divisors(Gmac *gmac)
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u8_t cns, acns, nit;
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min_cycles = SOC_ATMEL_SAM_MCK_FREQ_HZ;
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min_cycles = MCK_FREQ_HZ;
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min_period = NSEC_PER_SEC;
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for (i = 0; i < ARRAY_SIZE(mck_divs); ++i) {
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{
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int mck_divisor;
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mck_divisor = get_mck_clock_divisor(SOC_ATMEL_SAM_MCK_FREQ_HZ);
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mck_divisor = get_mck_clock_divisor(MCK_FREQ_HZ);
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if (mck_divisor < 0) {
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return mck_divisor;
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}
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cfg->config_func();
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#ifdef CONFIG_SOC_FAMILY_SAM
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/* Enable GMAC module's clock */
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soc_pmc_peripheral_enable(cfg->periph_id);
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/* Connect pins to the peripheral */
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soc_gpio_list_configure(cfg->pin_list, cfg->pin_list_size);
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#else
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/* Enable MCLK clock on GMAC */
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MCLK->AHBMASK.reg |= MCLK_AHBMASK_GMAC;
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*MCLK_GMAC |= MCLK_GMAC_MASK;
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#endif
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return 0;
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}
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#endif
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}
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#ifdef CONFIG_SOC_FAMILY_SAM
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static const struct soc_gpio_pin pins_eth0[] = PINS_GMAC0;
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#endif
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static const struct eth_sam_dev_cfg eth0_config = {
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.regs = GMAC,
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.periph_id = ID_GMAC,
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#ifdef CONFIG_SOC_FAMILY_SAM
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.pin_list = pins_eth0,
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.pin_list_size = ARRAY_SIZE(pins_eth0),
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#endif
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.config_func = eth0_irq_config,
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.phy = {GMAC, CONFIG_ETH_SAM_GMAC_PHY_ADDR},
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};
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#include <net/mii.h>
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#include "phy_sam_gmac.h"
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#ifdef CONFIG_SOC_FAMILY_SAM0
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#include "eth_sam0_gmac.h"
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#endif
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#define LOG_MODULE_NAME eth_sam_phy
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#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
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