This commit adds support for TF-M to the MPS2 AN521.
When the CONFIG_BUILD_WITH_TFM flag is set, a secure and
non-secure processing environment image pair will be
generated, with the Zephyr application image running on
the non-secure side.
The secure and non-secure binary images will be signed
for use with the BL2 secure bootloader.
An additional .hex file is also generated to enable
running QEMU with the AN521 binaries, `tfm_qemu.hex`,
which can be executed with the `-t run` option with
west, or `run` with ninja or make.
When configured for use with TF-M, the
`mps2_an521_nonsecure` board definition should be used.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
PSA level 1 requires secure boot. TF-M BL2 is the official
secure boot loader. It needs a BL2_HEADER_SIZE offset.
Align nonsecure address with TF-M's NS slot while TF-M BL2 enabled.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
For long lists of items, it's better to use a multi-column display to
make better use of the screen space. We used the hlist directive to
accomplish list, but it has a drawback on small (phone) screens because
under the hood, the rendering is done using tables.
Instead, we can take advantage of built-in CSS multi-column support
available in recent browsers. So, convert uses of the hlist directive
to use an rst-class directive to apply a multi-column class to
the entity. The chosen column-width (18em) gives us a 3-column display
on typical window sizes, but will adjust to more or fewer columns
depending on the actual real estate available.
Also, update the documentation guidelines to mention this change.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
This commit adds a note alluding to the fact that these two boards are
primarily included for use with QEMU, but have been tested on actual
hardware as well where appropriate.
Signed-off-by: Kevin Townsend <kevin@ktownsend.com>
This commit adds a note alluding to the fact that these two boards are
primarily included for use with QEMU, but have been tested on actual
hardware as well where appropriate.
Signed-off-by: Kevin Townsend <kevin@ktownsend.com>
The AN521 is a Soft Macro Model implementation of the SSE-200 subsystem
with SIE-200 and CMSDK components targeting the MPS2+ board. The
SSE-200 subsystem implements two Cortex-M33 cores.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
