- add NXP_BOARD_SPECIFIC_MPU_SETTINGS kconfig to provide a switch
for developer if they want to use private mpu settings
CONFIG_NXP_BOARD_SPECIFIC_MPU_SETTINGS==1 | NXP default setting
CONFIG_NXP_BOARD_SPECIFIC_MPU_SETTINGS==0 | User specific
- Use DT function to get memory base address and region size for cm7
- CM33 use dts to set mpu settings
- Add REGION_CUSTOMED_MEMORY_SIZE macro provide a common mapping ways
to map actual memory_size_kb to "region_size"
- The settings of the unified memory on cm33/cm7 cores:
ocram1/flexspi2 -> REGION_RAM_NOCACHE_ATTR
ocram2/dtcm -> REGION_RAM_NOCACHE_ATTR
flexspi/itcm -> REGION_FLASH_ATTR
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
This commit adds multicore support to copy CM33 CPU1 image
from flash to RAM where it will boot from.
Also added NXP_IMXRT_BOOT_HEADER=y for CPU0 so it can be booted
from FlexSPI Flash.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
The SDK code to handle managing Wakeup IRQ's for low power mode
varies between SoC's.
Add a MACRO that can be called by the Zephyr drivers so we
can manage these variations without adding SoC specific code
to the drivers.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Originally the driver is selected if `HAS_MCUX_SRC_V2` is
selected in SOC level kConfig.
Change to use dts to mark the driver is avaiable for some SOC.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Change hardware cycle count (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) to 594
MHz. Move that value to the SoC layer's DT.
Validated with the amp_blinky example - the period of the blinking LED
is exactly 2 seconds, like was programmed.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
For better organization, split the Kconfig files into one per each CPU.
Also, there was a bug where MFD was made to depend on flexcomm being
enabled, when really it probably meant to just default y if flexcomm is
enabled.
Leave Kconfig.soc in one file for the SOC.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Keep AHB clock running when CM7 is sleeping and TCM is accessible.
Otherwise, NETC transmission will fail.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Remove these legacy kconfig, not necessary.
The DT already has the bindings and nodes required to represent if there
is a FlexSPI and/or SEMC.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This Kconfig does not belong in the ADC folder, because there is not
actually a zephyr ADC driver for this. Also, remove HAS_MCUX_ADC_ETC as
well because it is a useless config.
The cmake line to pull in this driver from the SDK in the zephyr repo is
totally unnecessary. If a user wants to use this SDK driver they can add
it to their build like any other SDK driver or any other
external code module. Zephyr should not be a cesspool of random build
glue for random pieces of code.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The only code change to remove this was a redundant usage in the rt1180
soc.c which was not needed because it was redundant, if you catch my
drift.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Remove the configs that are not actually used for anything anymore or
never were, or that are redundant with other configs, and don't have any
code changes outside of Kconfig to remove.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add support for executing the CM7 core directly from flash memory
(XIP - eXecute In Place) instead of copying to ITCM. This provides
the following benefits:
- Allows for larger code size than the 512KB ITCM limit
- Simplifies memory management for large applications
- Reduces boot time by eliminating the need to copy code to ITCM
The implementation includes:
1. A new Kconfig option CM7_BOOT_FROM_FLASH (default: n) to control
the execution mode
2. A device tree overlay (cm7_flash_boot.overlay) that configures
the flash memory for CM7 execution
3. Updates to soc.c to calculate the correct CM7 boot address
based on the flash partition
5. Documentation updates with instructions for both execution modes
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Remove INPUTMUX interrupt assignments for PINT and GPIO peripherals.
Remove gpio0 DT node.
As the GPIO peripherals can be secured on the mimxrt798s, accesses from
the cm33_cpu0 and hifi4 are mutually exclusive, so the GPIO0 will stay
enabled in the cm33_cpu0 domain.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Rename symbols so that they reflect purpose of defined memory regions.
Point region symbols to nodes in the DT. Move bogus IDT section before
DSP's ITCM. Move common ROM and RAM sections before the heap.
The move had to be done as these sections and the heap did overlap.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Add dummy interrupt controller, clock control, pin control, Flexcomm 0,
Flexcomm 2, SAI0, SAI1, SAI2 into SoC's DT. Enable relevant nodes in
board's DT and include pinctrl definitions. Add default LED and button
nodes. Set /hifi4's real frequency. Add memory nodes for device's main
SRAM.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Add desired Kconfig implications for the mimxrt798s/hifi4 domain. Add
pinctrl_soc.h and set up an include path for it.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Create Kconfig variable NXP_INPUTMUX, which selects the fsl_inputmux
driver. Imply the MCUX component symbol from it. Imply that variable
from the NXP PINT, SmartDMA and LPC DMA drivers and from the mimxrt685s
SoC.
This needed to be done for the mimxrt700_evk/mimxrt798s/hifi4 domain, as
the INPUTMUX peripheral handles IRQ assginments and its driver
(fsl_inputmux) is used directly by the domain's soc.c. Instantiating the
currently dependent drivers (for PINT and SmartDMA) isn's possible nor
reasonable on the said target.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Add needed backtrace helpders routines and enable
backtrace for the Xtensa Fusion F1 DSP in the
IMXRT595S.
Signed-off-by: Mike J. Chen <mjchen@google.com>
To reduce the SEMC clock to a usable speed we had to divide down
the output clock of System PLL2 PFD1. To do this I had to override
the hardcoded defaults. This commit adds the flexibility to
override them in your board files.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
Errata ERR050396 causes data corruption if writes happen to TCM memory
so work around it by not marking AXI transaction cacheable. Workaround
taken from NXP SDK example.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `soc` and `subsys` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Fix for compiling i2s drivers on the NXP mimxrt1010_evk board.
For mimxrt1011, the defines kCLOCK_Sai2... are not defined as the sai2
peripheral does not exist. Trying to compile gives error. Fixed by adding
check for device tree node around code that uses the defines. Also added
same for sai1 and sai3. Thanks @lucien-nxp, @ZhaoxiangJin from NXP.
Signed-off-by: Imran Sajjad <imran.sajjad@iconfitness.com>
Don't force select INIT_SYS_PLL at SOC level. Instead use default y so
that board can unset it. Keep previous case where we would default y
which was only on RT1040. Also, this config is not used in RT1170 soc,
so move it to RT10xx series kconfig instead of family level. And it
appears to be on all the RT10xx, so ifdef is not needed.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Don't force select the INIT_VIDEO_PLL config so that board level can
unset it. Also clean up the code a bit in soc.c files.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The LDO config should not be forcefully selected at SOC level. Instead,
use soft default y so that board definition can unset it if desired.
Also, in the soc.c, the LDO code should be on both the rt1160 and
rt1170, so the definitions should exist, and ifdef is not needed. So can
switch to IS_ENABLED to decrease configuration complexity of the source
code.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The DCDC should be on all the platforms and the functions and structs
should therefore be defined on all the platforms. So the ifdef is not
needed, we can remove it to increase code compilation coverage unity
across configurations slightly. Compiler should optimize out the block
when IS_ENABLED is false statically.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Don't forcefully select this config in SOC level. Make it softer default
y so board can unselect it.
The config should not be possible if there is no arm pll, namely on
RT101x and RT102x. So add dependency clause about this.
And of course, code for this was a mess, clean up a bit.
Also remove the ifdeffry for selecting a default value for the two SOCs,
because they already put the same default value in the SOC Devicetree
DTSI, so that code had no purpose as long as a board didn't completely
redefine the SOC DT.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Initial motivation for this commit was to not force select
the INIT_ENET_PLL config from SOC level to allow for board level
configuration which might want it to be off.
While doing that, I discovered that RT11xx actually does not have
anything called by "ENET PLL" in the reference manual. So I have
removed the config for RT11xx. The default clock source for this soc.c
code for RT11xx is PLL1 DIV2, which I changed to just be configured if
ethernet is enabled, which was the reason to configure this pll as it
stands now, even though it is not specific to ethernet (although the
DIV2 output is mostly for ethernet). Another config is therefore not
needed.
For RT10xx, the situation is a lot more complicated. There is a lot of
discrepancy again between what is considered the "ENET PLL" both
conceptually and literally between the RM, SDK, and Zephyr config. And
also the code to define the config struct was a complete mess. So I have
simplified the code and changed it so that the config is only a soft
default to y instead of selected forcefully. Also, for the case of the
RT1010 and RT1020 series, the SDK is appearing to configure PLL6 (again
there is no clear ENET PLL meaning on these platforms) 500M output
through this "enet pll" configuration function. So similarly instead of
always enabling this output for those platforms, I added a new config
which can be set or unset by board level.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Several reason cause loopback test failed:
a) FlexIO input frequency is not correct, on RT11xx, input freq is 24M,
while max baud rate can reach 1/4 of input freq, so it can only support
6Mbps.
b) Flexio shift register depend on correct timer output to triggger TX
and RX, if timer comparison value is not accurate, RX error happens on
high baud rate. This is the reason why test fails on RT1060.
also fix a error on FlexIO clock ID calculation.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
CS hold time parameter is not correct which may cause bus fault
randomly.
System hang during status register reading after flash progromming which
is caused by parameter accessing in XIP mode.
Add dummy delay for READ command according the flash datasheet which is
required for SDR mode.
Use FlexSPI internal divider for clock updating instead of register in
CCM to avoid potential risk caused by flash access during clock updating
procedure.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
The existing SAI diver cannot initialize the PLL on the
board, so the PLL settings will not be performed in the
driver.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Since the LPSPI drivers no long use MCUX at all, remove the MCUX
branding, to avoid confusion. In the future if an implementation uses
the MCUX SDK driver, it should specifically be called by MCUX in the
name.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add select for GEN_HANDLERS to use the more efficient
generated interrupt handlers.
Add select for HIFI3, which are the SIMD related registers.
Signed-off-by: Mike J. Chen <mjchen@google.com>
