RT7xx CM33 cores have D-cache enabled on SRAM by default. The SEGGER
RTT control block and ring buffers, when placed in regular .bss, are
held in D-cache after CPU writes and never reach physical SRAM that
J-Link reads — JLinkRTTViewer finds the control block (magic was
written before cache effects accumulated) but no buffer data ever
flows.
When CONFIG_USE_SEGGER_RTT=y, default CONFIG_SEGGER_RTT_SECTION_NONE=y
so the SEGGER source leaves the control block and buffers in plain
.bss subsections under -fdata-sections, then contribute an input
section snippet to the existing CONFIG_NOCACHE_MEMORY region pulling
_SEGGER_RTT, _acUpBuffer and _acDownBuffer into the MPU
non-cacheable area.
Reuses the Zephyr nocache infrastructure with zero SRAM overhead
when RTT is not enabled, and auto-sizes when buffer sizes change.
Verified on mimxrt700_evk/mimxrt798s/cm33_cpu0 with both
samples/basic/blinky (printf + CONFIG_RTT_CONSOLE=y) and
samples/subsys/logging/logger (CONFIG_LOG_BACKEND_RTT=y).
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Currently only LPSPI1 has a clock set. This clock seems to be way
larger than the max. allowable frequency of the LPSPI clock root
input. This change sets all the LPSPI instances to a valid clock.
The LPSPI clock root is set to PLL3 PFD2, which leads to a
fPERIPH clock of 135MHz, which is allowed on the RT11xx series.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
CONFIG_SMP is by default already not enabled,
so there is no need to set the default to n in the
soc or board specific Kconfig.defconfig
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Combine the Cortex-M7 ENET workaround updates into one commit.
- clear CACHE_ENET on i.MX RT11xx Cortex-M7 for ERR050396
- disable ETH_NXP_ENET_USE_DTCM_FOR_DMA_BUFFER by default on Cortex-M7
- keep the final Kconfig condition independent of
DT_HAS_NXP_ENET1G_ENABLED
This avoids touching the same Kconfig and SoC files in follow-up
commits while preserving the intended behavior for PR #106679.
Validation:
- branch history squashed so workaround files are updated once
in the series
Signed-off-by: Hake Huang <hake.huang@nxp.com>
Remove the whitespace from dt_has_compat. The whitespace would be part of
the compatible name and never match the device-tree. Therefore, this config
would never be enabled by the DT.
Also fix a typo in BOOT_XSPI_NOR's message.
Signed-off-by: Daniel Schultz <dschultz@baylibre.com>
Add support for the ODRIVE (output drive) field at bits 12-13 of the
IOPCTL register on RT7XX. This field controls the transmitter current
drive impedance selection (100/66/50/33 ohm).
- Add nxp,drive-current property to the rt-iocon-pinctrl binding
- Add IOPCTL_PIO_ODRIVE macro to pinctrl_soc.h
- Extend pin config mask from 0xFFF to 0x3FFF to include ODRIVE bits
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Update the help text for CONFIG_SECOND_CORE_MCUX to be more generic
and applicable to all supported multi-core RT series (RT11xx, RT118x,
and RT7xx), rather than being specific to RT11xx and Cortex-M7/M4.
The updated documentation now refers to "primary core" and "secondary
core" instead of specific core types, making it more accurate for all
supported SoC series.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add an RT118x ARM PLL binding wrapper that reuses the shared
loop-div/post-div schema and derive CLOCK_InitArmPll() directly
from devicetree.
RT118x keeps the new loop-div/post-div properties only and removes
the hard-coded loop and post divider values from the SoC init path
while retaining the HAL loop divider range check.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Replace the fixed-factor-clock compatible with an RT11xx ARM PLL
binding that shares the loop-div/post-div schema through a common
include.
The RT11xx wrapper keeps the deprecated clock-mult/clock-div
properties and the SoC code falls back per property so existing
definitions keep working while new overlays can switch to
loop-div/post-div.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
After commit b1afb494b0, zephyr,flash points to the
soc-nv-flash child node instead of the
nxp,imx-flexspi-nor controller. This shifts the DTS
hierarchy by one level, so
DT_PARENT(DT_CHOSEN(zephyr_flash)) now returns the
flash controller node, not the FlexSPI bus node.
Use DT_CHOSEN(zephyr_flash_controller) to directly
reference the flash controller, and DT_PARENT of it
to reach the FlexSPI bus where needed.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
RT1166 and RT1176 CM4 parts use the MCUX LMEM cache block
and expose both code and system-bus cache in their HAL
feature headers.
Select the LMEM cache driver path, advertise both ICACHE
and DCACHE, and default these CM4 builds to
CACHE_MANAGEMENT with the external cache driver.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Since RM1170 Rev. 5 the RC400 gate control bits are marked reserved.
Remove the call to CLOCK_OSC_GateOscRc400M since the headers need
updating to remove it completely as done with the RT1180.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
The image array entry in the boot container had incorrect values for
offset, size, and load_addr fields, preventing use with NXP Secure
Provisioning Tool (SPT).
The offset was calculated as -1 * CONFIG_IMAGE_CONTAINER_OFFSET
(0xFFFFF000) instead of CONFIG_CONTAINER_USER_IMAGE_OFFSET (0xA000).
The size and load_addr fields did not account for the header region.
These fields now correctly reflect the flash layout with container
at 0x1000 and application code at 0xB000.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
- Configure FLEXSPI2 root clock using SYS_PLL3_PFD2 with divider 2
when FLEXSPI2 is enabled and not used for XIP flash
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
BOARD_GrantTRDCFullPermissions() flow:
- Request TRDC ownership via ELE for AON/MEGA/WAKEUP
- Apply SDK-aligned DAC (including TRDC3 MDAC assignments)
- Grant full access control settings for TRDC1/TRDC2
Refactor the implementation out of soc.c into a dedicated trdc_setup.c
file to keep soc.c focused on early init sequencing, and add it to the
SoC CMakeLists.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
- Gate off M7 clock before clearing M7_CFG[WAIT] (CPUWAIT) and gate
it back on after the deassert. (This is the process requirement
in RT118X RM)
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
The RT1180 platform requires periodic communication with the EdgeLock
Enclave (ELE) to prevent system reset. According to RT1180 SRM section
3.11 "ELE active timer", the ELE must be pinged at least once every
24 hours.
This commit implements ELE ping functionality using Zephyr's software
timer API (k_timer). The timer is configured to ping the ELE every
23 hours (instead of 24) to account for potential clock inaccuracies.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
- Improve the universality of the 118x series SoC and
decouple the dependencies that point to specific parts.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
This commit adds cache handling for Hifi4 core on RT600.
Enable CACHE_MANAGEMENT and HAS_DCACHE.
This is required for proper data coherency when the DSP shares memory
with other cores (e.g., Cortex-M33) or DMA peripherals.
With this change, applications can now use sys_cache_data_flush_range()
and sys_cache_data_invd_range() to ensure cache coherency in shared
memory scenarios.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
1. This commit converts the 'XIP_BOOT_HEADER_DCD_ENABLE' preprocessor
define to Kconfig options across NXP i.MX RTxxxx evaluation boards.
The changes enable flexible boot header configuration through the
Kconfig build system instead of compile-time defines, improving
configurability and maintainability.
2. Now 'XIP_BOOT_HEADER_DCD_ENABLE' flag is only used in
hal_nxp/rtxxxx/fsl_flexspi_nor_boot.h which is included by soc.c,
therefore, this flag should be passed in the rtxxxx/SoC layer CMake
using zephyr_library_compile_definitions(). and can be removed from
each board CMakeLists.txt.
Note: if out-of-tree files still need to use this flag, please add
it in your own CMakeLists.txt.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
1. This commit converts the 'XIP_BOOT_HEADER_ENABLE' preprocessor
define to Kconfig options across NXP i.MX RTxxxx evaluation boards.
The changes enable flexible boot header configuration through the
Kconfig build system instead of compile-time defines, improving
configurability and maintainability.
2. Now 'XIP_BOOT_HEADER_ENABLE' flag is only used in
hal_nxp/rt11xx/fsl_flexspi_nor_boot.h which is included by soc.c,
therefore, this flag should be passed in the rt11xx/SoC layer CMake
using zephyr_library_compile_definitions(). and can be removed from
each board CMakeLists.txt.
Note: if out-of-tree files still need to use this flag, please add
it in your own CMakeLists.txt.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
For RT10xx and RT11xx, flag 'BOARD_FLASH_SIZE' is only used
in hal_nxp fsl_flexspi_nor_boot.h which is included by soc.c,
therefore, this flag should be passed in the SoC layer CMake
using zephyr_library_compile_definitions() to limit its scope.
Normally, 'BOARD_FLASH_SIZE' should not be used elsewhere.
If an out-of-tree user uses this flag elsewhere, please define
the flag yourself.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Create a dedicated Zephyr library for the imxrt11xx and
imxrt10xx SoC in CMakeLists.txt and move soc.c into it
(zephyr_library() + zephyr_library_sources(soc.c)).
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The boot container was using a non-standard symbol name
`__rom_start_address` for the ROM start address. This symbol
is not defined when build with `-DCONFIG_CMAKE_LINKER_GENERATOR=y`.
This commit use the symbol `__rom_region_start` which is
available for both cases.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
It is better to let the FLEXSPI2 memory region in the final
linker file be generated from dts, in this way user/developer
can place the data in the region in code more easily.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
If the stack is in ITCM, DTCM, or FlexRAM OCRAM, flexram_dt_partition()
may change its contents. The comment on flexram_dt_partition()
acknowledges that, stating that it's inlined because it "cannot use
[the] stack". But we currently call SystemInit(), which is not inlined
and does use the stack, prior to flexram_dt_partition()! Fix that issue
by reordering the calls.
It seems to me that flexram_dt_partition() would be safer as a
soc_early_reset_hook implemented in assembly, but this fix does work for
the moment. Tested on an i.MX RT1061, with the stack in FlexRAM OCRAM
and entering Zephyr with all FlexRAM allocated to ITCM and DTCM.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
If the stack is in ITCM, DTCM, or FlexRAM OCRAM, flexram_dt_partition()
may change its contents. The comment on flexram_dt_partition()
acknowledges that, stating that it's inlined because it "cannot use
[the] stack". But we currently call SystemInit(), which is not inlined
and does use the stack, prior to flexram_dt_partition()! Fix that issue
by reordering the calls.
It seems to me that flexram_dt_partition() would be safer as a
soc_early_reset_hook implemented in assembly, but this fix does work for
the moment. Tested on an i.MX RT1061, with the stack in FlexRAM OCRAM
and entering Zephyr with all FlexRAM allocated to ITCM and DTCM.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
LLEXT-related sections should only be added to the linker script when the
associated CONFIG_LLEXT is enabled. This has been done by checking for this
Kconfig symbol in every linker file, but this creates a lot of boilerplate
for no good reason.
Use the much simpler solution: move the check inside the common linker file
and remove existing "#ifdef CONFIG_LLEXT" checks in all linker files.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The ATOMIC_OPERATIONS_* Kconfig option is not a choice, so it does not
have a default. However, the file that determines which actual atomic
operations backend will be used does default to
ATOMIC_OPERATIONS_BUILTIN:
3e537db71e/include/zephyr/sys/atomic.h (L26-L41)
Since we want to ensure that all SoCs intentionally select the atomic
operations backend they want to use, select it at the SoC level for all
SoCs, as well as for the Cortex-M arch when the Armv8-M baseline profile
is selected.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Instead of gluing to the one in the HAL which is not very flexible to
configure, define the container header in the zephyr SOC code. This
fixes the bug of CONFIG_NXP_FLEXSPI_ROM_RAMLOADER not working.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Update include of header file arm_mpu_mem_cfg.h which has been moved
to a Cortex-M/-R-agnostic include directory.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
1. update hal_nxp to mcux sdk 25.09.00
2. Updated imxrt7xx part numbers to align with SDK.
3. Fixed typo in member of dsi_transfer_t structure. The sendDscCmd
and dscCmd shall be sendDcsCmd and dcsCmd.
4. Remove the call to the function 'CLOCK_OSC_GateOscRc400M'. This
function has been removed from the SDK.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add the #include <snippets-sections.ld> directive
to include a linker file automatically.
This file defines additional linker sections that
are dynamically added during the build process.
It is placed at the very end of the SECTIONS block,
ensuring that any sections it defines appear after
all standard sections.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
This commit adds cache handling for Hifi4 core on RT700.
Enable CACHE_MANAGEMENT and HAS_DCACHE.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
