For now, the logging subsystem is hidden from CDT to prevent freezing of
the IDE.
CLion has the same issue, where the IDE becomes slow with big RAM spikes.
Fortunately, CLion automatically defines a macro __JETBRAINS_IDE__ that we
can use
Signed-off-by: Giuliano Franchetto <giuliano.franchetto@intellinium.com>
Some device clock sources selection helpers were not correctly defined.
With this commit the definitions are updated to match the desciption
in the reference manual RM0453.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Picolibc inherited its malloc arena configuration from newlib instead of
from minimal libc. This ended up making it a bit too fragile to run the
full set of zephyr tests. In particular:
* Z_MALLOC_PARTITION_EXISTS would get set when not used
* Setting an arena size depended on a bunch of other values, including
whether the system had an MMU or MPU, and whether the MPU required
power-of-two alignment or not.
This patch cleans things up so that there is a single heap size specifier,
PICOLIBC_HEAP_SIZE.
* If PICOLIBC_HEAP_SIZE is positive, this sets the size of the heap. On
MMU systems, picolibc will only use the remaining memory if that's
smaller.
* If PICOLIBC_HEAP_SIZE is zero, then there is no heap available and
malloc will always fail. This also disables Z_MALLOC_PARTITION_EXISTS.
* If PICOLIBC_HEAP_SIZE is negative, then picolibc uses all remaining
memory for the malloc heap.
The defaults are designed to allow tests to work without requiring
additional settings.
* For MMU enabled systems, the default value is 1048576. It would be nice
to have this use 'all available memory', but that's difficult to manage
as the API which returns free memory (k_mem_free_get) doesn't take into
account the amount of free virtual address space.
* For MPU enabled systems which require power-of-two aligned MPU regions,
the default value is 64kB.
* For other systems, the default value is -1, indicating that all
available memory be used for the malloc arena.
Signed-off-by: Keith Packard <keithp@keithp.com>
Added functions which allow to use zero copy model for handling
data within the packet buffer.
Additionally, added handling of cache by adding option to keep rd_idx
in different cache line than wr_idx and data.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Strings in C++ are usually of type char[] instead of char*.
Therefore, this needs to be taken into account when doing
tagged arguments or else char[] would be tagged as simple
pointer. So fix this by adding a way to get the type of
elements in an array to determine if it is a char array.
Fixes#46761
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Updates the API and types to match updated I2C terminology. Replaces master
with controller and slave with target.
Updates all drivers to match the changed macros, types, and API signatures.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The i2c terminology has been updated as such master is now controller,
and slave is now target. Updates all doc comments and doc pages to use
updated terminology. Does not change types or API definitions.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
In performing a double check of Zephyr arm64 MMU config
against edk2, a different in the programming of the
Translation Control Register (TCR) was found. TCR.TG[1]
should be set to address Cortex-A57 erratum 822227:
"Using unsupported 16K translation granules might cause
Cortex-A57 to incorrectly trigger a domain fault"
Signed-off-by: Eugene Cohen <quic_egmc@quicinc.com>
The BT_CODEC_LC3_CONFIG_* macros had a hardcoded location
and context, which makes them a lot less usable.
Updates the macro, and the macros that used them.
This also removes the BT_CODEC_LC3_CONFIG and instead
just uses the BT_CODEC_LC3_CONFIG_N macro, which has
then been renamed to BT_CODEC_LC3_CONFIG.
As an addition, the macros and their input has
also been better documented.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
In LE Audio we both have Stream Context and Preferred Context.
Rename to make it more explicit what context should be supplied
to those macros.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
The scan response API is fairly unclear and it is not
mentioned that the scan recv callback is also for
scan responses. Added some additional text and
information for the scan callbacks.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
This commit introduces driver for granting access for own grant
table and for mapping/unmapping foreign gref. Grant tables are used
for data exchange between Xen domains via shared memory page(s) (e.g.
for sharing ring buffer with driver data) This functionality is
widely used and needed for implementing PV backend/frontend drivers.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
Schedules I/O chains in the same order as they arrive providing a fixed
amount of concurrency. The low memory cost comes at the cost of some
computational cost that is likely to be acceptable with small amounts
of concurrency.
The code cost is about 4x higher than the simple linear executor
which isn't entirely unexpected as the logic requirements are quite a bit
more than doing the next thing in the queue.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
A DMA friendly Stream API for zephyr. Based on ideas from io_uring
and iio, a queue based API for I/O operations.
Provides a pair of fixed length ringbuffer backed queues for submitting
I/O requests and recieving I/O completions. The requests may be chained
together to ensure the next operation does not start until the current
one is complete.
Requests target an abstract rtio_iodev which is expected to wrap all
the hardware particulars of how to perform the operation. For example
with a SPI bus device, a description of what a read, and write mean
can be decided by the iodev wrapping a particular device
hanging off of a SPI controller.
The queue pair are submitted to an executor which may be a simple
inplace looping executor done in the callers execution context
(thread/stack) but other executors are expected. A threadpool executor
might for example allow for concurrent request chains to execute in
parallel. A DMA executor, in conjunction with DMA aware iodevs
would allow for hardware offloading of operations going so far as to
schedule with priority using hardware arbitration.
Both the iodev and executor are definable by a particular
SoC, meaning they can work in conjuction to perform IO operations
using a particular DMA controller or methodology if desired.
The application decides entirely how large the queues are, where
the buffers to read/write come from (some executors
may have particular demands!), and which executor to submit
requests to.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Starting with Zephyr 2.1, the back-end must filter out all old entities
and call the callback with only the newest entity.
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
This commit is reworking clock definition in
order to match linux filetree and definition
as much as possible.
- dt-bindings: rework renesas clocks dt-bindings
- regroup renesas related dt-bindings in a folder
- rename renesas rcar common dt-binding to match linux name
- add soc specific dt-binding matching linux name
- soc dt-bindings are defining clocks matching linux names
- dts: use new clocks names
- move clocks definitions in SoC layer for each core clock entry
- driver: use new clocks names
As seen in this commit, we are declaring clocks for "R8A7795" SoC
to match linux names.
Linux is not declaring "R8A77951" SoC specific files because
its also supporting the first H3 SoC version numbered "R8A77950".
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
The generation of the software ISR table and the IRQ vector table
(respectively generated by CONFIG_GEN_SW_ISR_TABLE and
CONFIG_GEN_IRQ_VECTOR_TABLE) should (in theory) go through three stages:
1. A placeholder table is generated in arch/common/isr_tables.c and
placed in an orphaned .gnu.linkonce.{irq_vector_table, sw_isr_table}
section
2. The real table is generated by arch/common/gen_isr_tables.py (creating
the build/zephyr/isr_tables.c file)
3. The real table is un-orphaned by moving it in a proper section with a
proper alignment
While all the steps are done automatically for the software ISR table,
for the IRQ vector table each architectures must take care of modiying
its own linker script to place somewhere the generated IRQ vector table
(basically step 3 is missing).
This is currently only done for 2 architectures: Cortex-M (ARMv7) and
ARC. But when another architecture tries to use the IRQ vector table,
the linker complains about that. For example:
Linking C executable zephyr/zephyr.elf
riscv64-zephyr-elf/bin/ld.bfd: warning: orphan section
`.gnu.linkonce.irq_vector_table' from
`zephyr/CMakeFiles/zephyr_final.dir/isr_tables.c.obj' being placed in
section `.gnu.linkonce.irq_vector_table'
In this patch we introduce a new CONFIG_ARCH_IRQ_VECTOR_TABLE_ALIGN to
support the architectures requiring a special alignment for the IRQ
vector table and we also introduce a way to automatically place the IRQ
vector table in place in the same way it is done for the ISR software
table.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
STM32_DT_CLOCKS was designed to take a device tree node label name as
argument: STM32_DT_CLOCKS(uart1)
Change its implementation to take a node identifier instead:
STM32_DT_CLOCKS(DT_NODELABEL(uart1)).
This make its usage more flexible since the argument can now be extracted
from other DT macros such as DT_PARENT. Then, the following can be done:
STM32_DT_CLOCKS(DT_PARENT(child_node_label)).
Since it is now possible implement STM32_DT_INST_CLOCKS using
STM32_DT_CLOCKS.
Finally, update existing STM32_DT_CLOCKS users and convert
STM32_INST_CLOCK_INFO users to STM32_CLOCK_INFO.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Riscv platfrom includes linker dt regions (LINKER_DT_REGIONS)
but was missing functionality to generate linker sections
from zephyr,memory-region dt nodes.
Signed-off-by: Lukasz Stepnicki <lukasz.stepnicki@nordicsemi.no>
Picolibc already provides the functionality offered by cbprintf, so
there's no reason to use the larger and less functional version included
in zephyr.
Signed-off-by: Keith Packard <keithp@keithp.com>
Adds a small macro to help people get the dma buffer alignment
property for a particular DMA controller.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Simple driver that allows one to choose the clock speed of xtensa cores.
It's basically a shim layer on top of SOC level driver.
Also, a really simple test case was added, mainly to ensure things are
build and are sane.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Document POSIX wrappers for socket operations, by referencing a
corresponsding `zsock_*` function. The documentation will generate a
link where user can read the actual documentation on the socket
operation.
In order to include the POSIX wrappers in to the documentation however,
it's needed to add CONFIG_NET_SOCKETS_POSIX_NAMES to predefined symbol
list in zephyr.doxyfile.in.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Some services require the ability to query whether a GPIO pin
is configured as an input, output, both, or neither prior to
performing any operations at the service level. This is done
in order to reduce state tracking within the service.
To that end, this change adds
* `gpio_port_get_direction()`
* `gpio_pin_is_input()`, and
* `gpio_pin_is_output()`
Signed-off-by: Christopher Friedt <cfriedt@fb.com>
The __unused attribute is the preferred way of marking
a variable as unused when assertions are disabled.
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
Renaming objects which had 2 in the name to indicate that
it is v2 specific. Once logging v1 has been removed such
suffixes are redundant.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Triggers CPU exception with illegal instruction when z_except_reason
is called (e.g. in k_panic, k_oops). Creates exception stack frame
for use by coredump. Adds unique cause code for ARCH_EXCEPT. Disables
test case failure for qemu_xtensa.
Without an ARCH_EXCEPT implementation, z_except_reason calls
z_fatal_error directly with a null ESF and bypasses
xtensa_excint1_c's error logging. An ESF is required to coredump.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
This reverts the bulk of commit c8bfc2afda ("riscv: make
arch_is_user_context() SMP compatible") and replaces it with a flag
stored in the thread local storage (TLS) area, therefore making TLS
mandatory for userspace support on RISC-V.
This has many advantages:
- The tp (x4) register is already dedicated by the standard for this
purpose, making TLS support almost free.
- This is very efficient, requiring only a single instruction to clear
and 2 instructions to set.
- This makes the SMP case much more efficient. No need for funky
exception code any longer.
- SMP and non-SMP now use the same implementation making maintenance
easier.
- The is_user_mode variable no longer requires a dedicated PMP mapping
and therefore freeing one PMP slot for other purposes.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
5f65dbcc9dab3d39473b05397e05.
The tp (x4) register is neither caller nor callee saved according to
the RISC-V standard calling convention. It only has to be set on thread
context switching and is otherwise read-only.
To protect the kernel against a possible rogue user thread, the tp is
also re-set on exception entry from u-mode.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This patch adds the new trigger types SENSOR_TRIG_MOTION
and SENSOR_TRIG_STATIONARY to distinguish these common
motion detection events.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Logging v1 has been removed and log_strdup wrapper function is no
longer needed. Removing the function and its use in the tree.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Return the hardware mpid value directly. Guard against values that
wouldn't fit in the returned uint32_t. If that ever happens then
reverting to the Zephyr sequential CPU number should be considered.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
the CSIS client now has a ordered access procedure function.
The function implements the procedure as per the CSIP spec,
where it will verify that 1 or more members are unlocked,
and the execture a procedure on each member in ascending
order of rank.
The procedure can be anything (even a non-BT procedure),
and it will be up to the applicaiton to implement
what to do in that.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Having the members array being const causes a lot of
limitations in the implementatation, and was
occasionally even disregarded. Removed to make the
implementation more flexible.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
This commit adds new functions, which can be used for Xen event channel
management (allocation, interdomain binding etc.). Such functionality
is needed for Xen PV driver development in Zephyr.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
Picolibc is a fork of newlib designed and tested on embedded systems. It
offers a smaller memory footprint (both ROM and RAM), and native TLS
support, which uses the Zephyr TLS support.
By default, the full printf version is included in the executable, which
includes exact floating point and long long input and output. A
configuration option has been added to switch to the integer-only
version (which also omits long long support).
Here are some size comparisons using qemu-cortex-m3 and this application
(parameters passed to printf to avoid GCC optimizing it into puts):
void main(void)
{
printf("Hello World! %s %d\n", CONFIG_BOARD, 12);
}
FLASH SRAM
minimal 8696 3952
picolibc int 7600 3960
picolibc float 12304 3960
newlib-nano int 11696 4128
newlib-nano float 30516 4496
newlib 34800 6112
---
v2:
Include picolibc-tls.ld
v3:
Document usage in guides/c_library.rst and
getting_started/toolchain_other_x_compilers.rst
v4:
Lost the lib/libc/picolibc directory somehow!
v5:
Add PICOLIBC_ALIGNED_HEAP_SIZE configuration option.
Delete PICOLIBC_SEMIHOST option support code
v6:
Don't allocate static RAM for TLS values; TLS
values only need to be allocated for each thread.
v7:
Use arm coprocessor for TLS pointer storage where supported for
compatibility with the -mtp=cp15 compiler option (or when the
target cpu type selects this option)
Add a bunch of tests
Round TLS segment up to stack alignment so that overall stack
remains correctly aligned
Add aarch64 support
Rebase to upstream head
v8:
Share NEWLIB, NEWLIB_NANO and PICOLIBC library configuration
variables in a single LIBC_PARTITIONS variable instead of
having separate PICOLIBC_PART and NEWLIB_PART variables.
v9:
Update docs to reference pending sdk-ng support for picolibc
v10:
Support memory protection by creating a partition for
picolibc shared data and any pre-defined picolibc heap.
v11:
Fix formatting in arch/arm/core/aarch64/switch.S
v12:
Remove TLS support from this patch now that TLS is upstream
Require THREAD_LOCAL_STORAGE when using PICOLIBC for architectures
that support it.
v13:
Merge errno changes as they're only needed for picolibc.
Adapt cmake changes suggested by Torsten Tejlmand Rasmussen
v14:
Update to picolibc 1.7 and newer (new stdin/stdout/stderr ABI)
v15:
Respond to comments from dcpleung:
* switch kernel/errno to use CONFIG_LIBC_ERRNO instead of
CONFIG_PICOLIBC
* Add comment to test/lib/sprintf as to why the %n test
was disabled for picolibc.
v16:
Switch picolibc to a module built with Zephyr. This eliminates
toolchain dependencies and allows compiler settings for Zephyr
to also be applied to picolibc.
v17:
Provide Zephyr-specific 'abort' implementation.
Support systems with MMU
v18:
Allow use of toolchain picolibc version.
v19:
Use zephyr/ for zephyr headers
v20:
Add locking
Use explicit commit for picolibc module
v21:
Create PICOLIBC_SUPPORTED config param. Set on arc, arm, arm64,
mips and riscv architectures.
Signed-off-by: Keith Packard <keithp@keithp.com>
There are few cases where removing this enforcement is desirable:
- linking against binary C++ libs with incompatible type mangling
- linking against system provided headers i.e. native_posix
- compiling with legacy code that assumes a different convention
So let's create a Kconfig symbol for it. This is IMHO a good compromize
compared to using the %"PRId32" abomination everywhere otherwise.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Added start, stop and update to the shell.
Refactored the event_cb of the rd_client_info struct into the ctx,
as it was needed in the shell script.
Signed-off-by: Ola Tangen Kulseng <ola.kulseng@nordicsemi.no>
Return the hardware hartid value directly.
Redefine arch_curr_cpu() in terms of arch_proc_id() to remove
the hartid reading duplication. The code assumed a linear hartid
space already so add a comment to that effect.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
When CONFIG_GEN_IRQ_VECTOR_TABLE and CONFIG_GEN_SW_ISR_TABLE are enabled
the generate IRQ table is trying to reference the _isr_wrapper function.
Add an extern to that to avoid a failure when compiling and remove the
previous arch-specific declarations.
arch/common/isr_tables.c:48:38: error: '_isr_wrapper' undeclared here
(not in a function)
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
All STM32G0 SoCs have two sets of APB registers(APB1 and APB2).
Therefore set STM32_PERIPH_BUS_MAX to 0x40 (STM32_CLOCK_BUS_APB2)
for this series.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
