Add USART1 and LPUART1 nodes on stm32wb series.
Only these 2 ones are available for now on this series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add GPIO support to stm32wb series.
Only ABCDE and H ports are available for now on this series.
Accordingly, update series dtsi file.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support to stm32wb series in stm32 clock_control driver.
Ip is similar to stm32l4 one but AHB bus presacler is renamed
to "CPU1" and CPU2 and AHB4 prescalers should be defined.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Implementation of AMS (Austria Micro Systems) ENS210 temperature and
relative humidity sensor.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
Add driver support for Atmel SAM0 device ID, which is 16-bytes long.
The device ID can simply be read from memory at a known location, but
the location is only described in the data sheet, not in ASF.
For SAMD2x it's 0x0080A00C, 0x0080A040, 0x0080A044 & 0x0080A048.
For SAMD5x it's 0x008061FC, 0x00806010, 0x00806014 & 0x00806018.
This adds a new property to the device tree to define the device ID
registers for this SoC family.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Add driver and device tree binding for the Low Power Inter-Integrated
Circuit (LPI2C) controllers found in the RV32M1 RI5CY SoC.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit adds CAN support for nucleo F746zg.
Furtermore CAN was added in stm32f7.dtsi and pinmuc_stm32f7.h
CAN_RX: PD0, CAN_TX: PD1
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
Add support for pulsing the hardware reset pin of the FXOS8700 high
during initialization.
According to the datasheet, this is required for the I2C/SPI bus
auto-detection logic to work properly if the VDD/VDDIO power
sequencing order cannot be guaranteed.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2 identical packages were defined for stm32f412 SoC, invariant "g".
Merge them in new sinclge stm32f412Xg.dtsi.
Update matching boards accordinlgy.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Allows to enable initial RTS/CTS hardware flow control
in the dts.
Co-authored-by: Benoit Leforestier <benoit.leforestier@gmail.com>
Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
Adjusted the MCP2515 driver to switch from KConfig SPI configuration to
DTS based configuration.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
The MCP2515 is a CAN controller that can be connected via SPI to an
host MCU. This driver adds support for the MCP2515 as a new driver in
the CAN subsystem.
As it is a SPI peripheral it uses a thread for its interrupt
handling and the received message filtering is done inside this
interrupt thread, as the MCP2515 filter capabilities are not sufficient
for the Zephyr CAN interface.
The driver was validated with an external CAN logger and the adjusted
CAN sample application.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Enable the clock for GPIO ports on the RV32M1 SoC before attempting to
access the port controller registers.
Fixes: #15339
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
SAMD20 does not have the DMA or USB peripherals and as a result
the IRQs for all subsequent lines are shifted down from SAMD21.
This splits the interrupt assignment for the SERCOMs into the
SoC specific DTS file and moves the USB definition to SAMD21 only.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
The SYSCFG_CFGR1_PA11_PA12_RMP define is present even on packages where
the remap isn't strictly required. This commit makes the remap optional
based on a DT property.
Also fixes syntax error caused by a missing );.
Signed-off-by: Josef Gajdusek <atx@atx.name>
The erase-block-size and write-block-size are needed for the spi_nor
driver to compile.
scripts/dts/extract/flash.py automatically adds these properties if
this flash device is part of the "chosen" flash node, but they're
otherwise missing.
Signed-off-by: Jim Paris <jim@jtan.com>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Ports B and C share a common interrupt vector on kw40 and kw41z socs,
but we don't currently have a way to express this in device tree. A
check was added in commit 77cb942a97 that
correctly causes build errors on kw40/41 boards when both ports are
enabled.
Disable the port b interrupt for now until we have a better way to
handle this.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
According to nrf51 and nrf52 specifaction every peripheral is
assigned a fixed block of 0x1000 bytes. Due to that dts for
nrf51 and nrf52 chips have been updated.
The only exception is gpio for nrf52840 where gpio0 and gpio1
share the same memory regions. For this reason, the definition
of gpio for nrf52840 is different from the others.
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
On various stm32 soc packages CCM is available and SRAM size
mentionned in datasheet include CCM.
Though, actual SRAM size defined in dtsi files should not
include CCM sizes.
Fix this on impacted dtsi files.
Fixes#14779
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The iMX RT1060 and RT1064 have additional dedicated 512KB on-chip ram.
This OCRAM2 is mapped at 0x20200000, formerly OCRAM1 (flexram) mapping
which is moved to 0x20280000 in order to guarentee global OCRAM memory
continuity regardless OCRAM1 size configuration (256KB by default).
In default configuration, this gives 768KB (512+256) on-chip ram:
0x20200000 to 0x202BFFFF.
OCRAM2: 0x20200000 - 0x2027FFFF
OCRAM1(FlexRam): 0x2028FFFF - 0x202BFFFF
Add this memory region as a single node in the rt1060 device tree.
Note: MPU expects power of two memory region, in case of 768KB, let
the MPU configure 1MB instead.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
uart4 is not available on whole stm32f4 series (not on stm32f401
for instance), remove from stm32f4.dtsi
It is actually correctly defined in f405, f413 but missing in f446,
so add it in there.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
1. SW PWM device node added to common nrf5_common.dtsi
2. SW PWM node set in all nRF5x DTSI files.
Different initial settings for nRF51 and nRF52 devices.
Status is ok by default for nRF51.
3. Added yaml binding for Nordic SW PWM node.
4. Set codeowner of nordic dts bindings to @anangl
Signed-off-by: Gaute Gamnes <gaute.gamnes@nordicsemi.no>
After commit 'scripts/dts: Never ignore properties in
generate_node_defines()', pointless entries for 'interrupt-names'
properties show up in generated_dts_board.conf and
generated_dts_board_fixups.h, because many bindings specify
'generate: define' for 'interrupt-names'.
If 'generation: define' is taken as "generate #define's for this
particular property", then only the 'interrupts' property ought to have
'generation: define'. Having it on both 'interrupts' and
'interrupt-names' makes you wonder what it would mean to only have it on
one of them.
Things get a bit confusing since 'interrupt-names' is still used when
determining the macro names generated for 'interrupts', but it's
probably best to have 'generation: define' work in a consistent way
still (and never be a no-op).
Remove 'generation: define' from all 'interrupt-names' bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
In the recent MDK brought by nrfx 1.6.2, these legacy peripherals have
been revealed as available also in nRF52810. This patch allows their
use in Zephyr drivers.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
On currently supported stm32f3 chips,
erase-block-size = 2048
write-block-size = 2
Set these property in stm32f3 series root dtsi file.
Fixes#9686
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The 'partition\d+:' definition might be a leftover from an older way of
handling partitions. There are no 'partition[0-9]' properties anywhere
in the DTS files.
The reason I want to get rid of this is that it's the only place where
you get a 'properties:' nested inside inside a 'properties:'. That's an
undocumented feature, and removing it will make generate_node_defines()
much simpler (non-recursive).
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
- Regexes (e.g. 'pinctrl-.*') are supported in property names in
bindings, but it was undocumented
- Remove the mention of 'generation: structure'. The only implemented
output format is #define's.
- Clean up the language a bit and move related stuff so that it appears
together
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Add nvs support to nucleo_f091rc board. This requires to
add erase-block-size property to stm32f0.dtsi.
Storage partition is set to 4kb at the end of the flash.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Initial support for Microchip MEC1701 series is incorporated to the
tree. Additional support for UART is also included. This SOC supports
two operation modes for interrupts (Direct and Aggregated). For this
commit, the interrupts are configured in direct mode.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
Add support to STM LIS2DW12 3-axis accelerometer driver.
The driver support I2C and SPI bus communication and both
polling and drdy trigger mode.
Co-authored-by: Mario Tesi <mario.tesi@st.com>
Signed-off-by: Armando Visconti <armando.visconti@st.com>
We've removed all references to base_label in dts bindings and are
removing the functionality. We should depend on DT_ prefixed defines
going forward.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
