Add i.MX93 Cortex-A Core support on Zephyr.
i.MX 93 applications processors deliver efficient machine learning
(ML) acceleration and advanced security with integrated EdgeLock
secure enclave to support energy-efficient edge computing.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The interrupt-map property specifies both 32-bits values and a phandle;
update the type accordingly.
Update the definition of pcie-host-ecam-generic on qemu arm64 to match
the new type.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Add DTS information for qemu-virt-a53 and qemu-kvm-arm64 for PCIe
controller support. Three new bindings are required for the PCIe
controller in ECAM mode.
The DTS information was extracted from QEMU (dumpdtb) with a PCIe device
attached to the virtual machine (ivshmem)
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
This is an AArch64 board. We also add RK3399 SoC support,
as well as a very simple Synopsys 8250dw UART driver.
Signed-off-by: Henri Xavier <datacomos@huawei.com>
Some reg size in fvp-aemv8r.dtsi isn't correct. This commit is used to
fix it.
- gic, the correct reg size is 0x10000 and 0x200000.
- uart0-3, the correct reg size is 0x10000.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano
applications processor, composed of a quad Cortex®-A53 cluster
and a single Cortex®-M47 core.
Zephyr OS is ported to run on the Cortex®-A53 core.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
1. Enable all cpu cores in soc dts and disable unused core in board dts.
2. Use default irq priority for uart interrupt.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
This patch is to add Cadence QSPI NOR flash device tree element
for the Cadence QSPI NOR flash driver bringup
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
This patch is to increase kernel VM size to 1.5MB and
memory size to 2MB to ready for future driver bring up.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
This patch is to enhance the uart ns16550 driver to get clock frequency
from clock manager or devicetree if clock_frequency is defined.
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
This patch is to enable arm timer driver for Intel Agilex SoC FPGA.
The PPI's interrupt ID will be mapped into the interrupt ID
defined by SBSA in GIC-400 controller.
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
The armv8 timer, arm gic, and arm gic-v3-its don't use or need the
devicetree label property. Update the dts bindings to not require it and
remove setting of the label property in dts files.
Signed-off-by: Kumar Gala <galak@kernel.org>
The ns16550 flags reg-shift property as optional. In case it is not
supplied, the ns16550 driver relies on a value defined in <soc.h>, or,
by default it takes 4 (shift by 2).
This patch adds the property to all ns16550 nodes, with the following
values:
- 2 if SoC did not have any custom value defined by
UART_REG_ADDR_INTERVAL (corresponds to 1 << 2 = 4)
- If SoC defined DEFAULT_REG_INTERVAL (snps_arc_iot/it8xxx2), use such
value (4=2, 2=1, 1=0).
These changes will allow simplifying the ns16550 driver.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add partial pin control support for the imx8mp. Since the UART driver is
not currently enabled, pin control cannot be tested on this platform.
Therefore, only the DTS definitions required to set the pinmux options
are present for this platform, and are not being applied (since
CONFIG_PINCTRL=n).
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add initial pin control support for the A53 core of the imx8mm. Since
the UART console driver is not currently enabled for this platform,
there is no way to test the full pin control enablement. Therefore,
CONFIG_PINCTRL is still not selected for this platform, although the
required DTS definitions and pin control headers are present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In order to bring consistency in-tree, migrate all dts code to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
fvp-baser-aemv8r has four pl011_uart devices and all of then have
been added in this patch.
only uart0 and uart1 are enabled as default in fvp_baser_aemv8r.dts
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
rename IMX_CCM_UART_CLK to IMX_CCM_UART4_CLK and
IMX_CCM_UART2_CLK a53 dtsi.
This was missed in a previsous patch set.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Fix the interrupt setting in the fvp_baser_aemv8r dts:
- The correct interrupt number is 5, not 0.
- The interrupt priority and type are swapped.
This patch also enables interrupt driven mode for this platform as this
is the ideal setting for a Fast Models based platform.
Issue-ID: SCM-4037
Signed-off-by: Filipe Rinaldi <filipe.rinaldi@arm.com>
Change-Id: Ic4815f5afe4c9df9d8fe373d47d2773d64087c96
The qemu arm64 virt machine PCIe controller config space needs a
64bit adressing, so switch the entire qemu-virt-a53 and
qemu_cortex_a53 board dts to address-cells & size-cells to 2
to accommodate for 64bit addresses.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Pick those common node in 'fvp-baser-aemv8r.dts' to 'fvp-aemv8r.dtsi'
which reside in 'dts/arm64/fvp-aemv8r' directory.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Add device tree for Intel SoC FPGA Agilex initial bring up. This is the
first version of device tree which enable single CPU core and basic
drivers that needed by hello_world example.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
1. add a seperate 2 cores SMP board configuration to run in Jailhouse
inmate Cell, root Cell Linux will use Core0 and Core1, Zephyr will
run on Core2 and Core3.
2. Refine the code of dts, move SoC common dts nodes into dtsi fiel in
dts/arm64/nxp/ directory.
3. Add myself to be code owner of directory dts/arm64/nxp/.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Currently the SRAM location is fixed for all the boards derived from
qemu_cortex_a53. While this is acceptable when the image is directly
loaded in SRAM by QEMU, in some cases Zephyr can be loaded in RAM by
another piece of software or by semihosting at a different address
before jumping into it.
When for example TF-A is used and Zephyr is run as BL33 payload using
QEMU, in this case the default location in RAM is at a different
address (when preloaded BL33 base address is not used).
To address these cases, move the SRAM location into the board-specific
DTS so that it can be adjusted on a board by board basis.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Split ARM and ARM64 architectures.
Details:
- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
(arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
boards/bcm_vk/viper directory
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
