In file stm32l412.dtsi, spi2 was missing fifo compatibility,
this way failing to initialise fifo threshold correctly
when spi data width is configured.
Signed-off-by: Mirko Bottarelli <mirko.bottarelli@gmail.com>
Add rng definition to f410.
Though, don't inherit directly in f412 as it's integrated
in a different way.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to ease description of DCKCFG regsiters,
make f412 a variant of f410 as it supposed to be.
Only exception is missing DAC1.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit adds the support for host commands being transported
by the Serial Host Interface on the NPCX SoC.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Add the st,static-prescaler DTS property to the
stm32u5 family on the LPTIM1.
Also present on lptim3, 4 but not defined yet.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Purpose of this node is only to provide a way to configure RF
clock using device tree and clock_control driver.
Default configuration is reproducing existing hard-coded configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add missing interrupts property for second FlexSPI device on RT5xx.
This interrupt is shared between both FlexSPI devices, but the memc
driver does not use interrupts so no conflict should arise.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The addresses of the flash and flash controller of the RP2040
SoC were mixed up. There was no clear distinction between the
flash and the flash controller, which was unclear but also
caused a DTC warning.
This commit makes the distinction clearer: The SSI peripheral at
0x18000000 is the flash controller, and the flash itself starts
at 0x10000000. The flash driver and rpi_pico.dts were fixed
accordingly.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
The pinctrl node of the RP2040 had the same unit address as the GPIO
bank, causing a DTC warning. To fix this, the pinctrl's address was
removed, as it does not require any.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Remove the test clock out Kconfig from SoC level. Instead use
device tree PINCTRL entry with updated clock control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add support for Microchip MEC15xx to the XEC clock control driver.
MEC15xx 32KHz clock support uses the same 32KHz source for both the
PLL and peripherals. MEC152x does not include the PCR clock monitor
present in MEC172x. MEC15xx and MEC172x support internal silicon
oscillator, parallel and single ended crystal inputs, and the
32KHZ_PIN input. MEC152x supports fall back to internal silicon
OSC when VTR and 32KHZ_PIN are turned off. Therefore in MEC152x the
internal silicon oscillator can only be disabled if using an external
32KHz which is always on. For MEC152x the driver will only use the
PLL source clock device tree value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Fix Microchip XEC clock control driver single-ended XTAL2 pin
initialization. Add support for external 32KHZ_IN pin as a
clock source including PINTRL to switch the GPIO to 32KHZ_IN
function. Add device tree option to disable internal silicon
oscillator if it is not required by the configuration. Add
device tree tuning options based on crystal and board layout.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add initial support for gd32l23x series. gd32l23x used Cortex-M23, based
on ARMv8-M baseline, implement the System Timer.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
Enable RTU.SWT (Real-Time Unit.Software Watchdog Timer) instances on
s32z270dc2_r52 boards. Module clock frequency is fixed to 48 Mhz.
Signed-off-by: Quang Bui Trong <quang.buitrong@nxp.com>
Add missing I2C clock sources for STM32F303 & F373.
Add a comment for all STM32F3 I2Cx and for STM32F0 I2C1 that the clock
source should always be defined.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add config cell property to gd,gd32-dma.
For supporting hardware variation, Splitting base definition
to gd,gd32-dma-base.yaml.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Define SYSCLK as the default I2C source clock for I2C1 on STM32F0x
and all I2Cx on STM32F3x.
On most series, the default I2C clock source (when it exists) is PCLK.
This clock does not exist as I2C clock source on FO & F3 and the default
one is HSI. Since HSI is not necessarily enabled we explicitly set it
to SYSCLK instead.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Include the new clock file dedicated for STM32F7 instead of the F4 one
previously used.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
peripheral-id property should be eventually removed.
For now set it as optional and allow skipping the usage
in UART driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
peripheral-id property should be eventually removed entirely.
For now set it as optional and allow skipping the usage
in GPIO driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
HAL update affects also EFR32MG21 SoC. Because of that we need to
update the reg addresses in DTS.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
This commit adds support for Silicon Labs EFR32BG22 SoC.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The ADC module has four conversion groups, each one is set up as a zephyr
device. The start-up calibration is initiated globally for all groups
and it is run in each device init function. The ADC module supports post
calibration per group. Post calibration is run automatically after each
group acquires the samples.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
The stm32G0 device has a one APB peripheral clock bus
but splitted on two RCC registers: RCC_ABPENR1 and RCC_ABPENR2
Peripherals are on one or the other.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.
This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.
The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
We are about to add UART reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
We are about to add timer reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
