The USB CDC driver is unable to process any bulk IN transfers
after receiving spurious 'Clear Feature - Endpoint Halt' request
from host due to perpetual locked state caused by previously
scheduled transfer, that will never be finished, as the endpoint's state
is set to NAK. Fix by ignoring spurious request.
Signed-off-by: Piotr Ciura <piotr.ciura@hidglobal.com>
- Reset specific configuration bits in
USB1_HS_PHYC->USBPHYC_CR before setting new values.
- Set the Frequency Selection (FSEL) bits to operate
the USB PHY Control Register at 24 MHz for proper communication.
- Enable the OTGPHY1 peripheral clock using LL_AHB5_GRP1_EnableClock.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
- Removing the unused declaration of 'ret'
in the usb_dc_stm32_init function for STM32N6.
- Ensuring the 'ret' variable is used correctly
in the pinctrl_apply_state function call.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
- Unified the handling of USB OTG HS and USB OTG FS
by removing redundant preprocessor conditionals.
- Introduced a new macro `UDC_STM32_BASE_ADDRESS`
to dynamically set the USB base address.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Enable clock and power for the OTG HS peripheral
of the STM32N6x serie
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Updated USB_DC speed definition macros for STM32 series
to handle different speed configurations
based on the SoC compatibility.
Added conditional checks for full-speed definitions
using DT_HAS_COMPAT_STATUS_OKAY for st_stm32_usb.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
Add defines to avoid magic values in the dtsi.
Replace usb_dc_stm32_get_maximum_speed() with device tree property.
- Use DT_INST_STRING_UPPER_TOKEN(0, maximum_speed) to set the USB speed.
- Remove PCD_SPEED_FULL initialization.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Implement the HAL callback function `HAL_PCD_ISOINIncompleteCallback` in
which the endpoint write semaphore is given back, thus allowing subsequent
writes to the endpoint after an isochronous transfer has been incompleted
(not read by the host).
This approach was chosen because it is similar to what is done in the
already implemented HAL callback `HAL_PCD_DataInStageCallback` which also
gives the write semaphore back but also calls the endpoint callback
function.
The reason for not also calling the endpoint callback function is because I
do not see any appropriate cb_status (`enum usb_dc_ep_cb_status_code`) to
pass. If passing `USB_DC_EP_DATA_IN` is okay even though "In transaction
done on this EP" is not completely true, then this should also be added.
This has been tested by setting up an isochronous endpoint, writing to it,
and verify that `HAL_PCD_DataInStageCallback` is called and subsequent
writes are possible.
Signed-off-by: Algot Axelzon <algot.axelzon@satcube.com>
Introduce new binding "st,stm32u5-otghs-phy" for OTG_HS PHY. This allows to
configure clock source and handle STM32U5 specific OTG_HS PHY behavior in
driver implementation in a more readable way.
Move OTG_HS PHY clock selection (previously <&rcc STM32_SRC_HSI48
ICKLK_SEL(0)>) from OTG_HS node to OTG_HS PHY node.
Rename USBPHYC_SEL -> OTGHS_SEL which matches the definition in the stm32u5
CCIPR2 register (RM0456 Rev 5, Section 11.8.47).
Support enabling OTG_HS PHY clock, which is bit 15 (OTGHSPHYEN) in
RCC_AHB2ENR1. Change OTG_HS clock to be bit 14 (OTGEN).
Calculate in runtime OTG_HS PHY clock source frequency. Try to match that
to supported (16, 19.2, 20, 24, 26, 32 MHz) frequencies and select proper
option with HAL_SYSCFG_SetOTGPHYReferenceClockSelection() API (instead of
hardcoded 16 MHz selection).
Co-authored-by: Adrian Chadd <adrian.chadd@meta.com>
Signed-off-by: Adrian Chadd <adrian.chadd@meta.com>
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Force disabling the USB OTG HS and PHY clock during sleepmode
By default, that clock is enabled by clock gating during sleep
mode. Like stm32H7, it has to be kept running.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Special sequence to enable clock and power for the OTG HS
peripheral of the stm32U59x serie
This code is based on the stm32Cube HAL_HCD_MspInit/DeInit.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
cbprintf_package complains about char usage for %p
string argument and suggests void * usage.
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
- If the peripheral is OTG_HS with ULPI, enable the OTG_HS ULPI clock
- The constant has a slightly different name on stm32h7
- Otherwise, if the peripheral is OTG_HS:
- Disable the OTG_HS ULPI clock in sleep/low power mode,
- If the peripheral is OTG_HS with PHYC[1], enable the PHYC clock.
- Otherwise, if the peripheral is OTG_FS[2] on stm32h7, also disable the
OTG_FS ULPI clock in sleep mode (in the device/ driver, this is done in
usb_dc_stm32_init()),
[1]: Internal HS PHY in stm32f7x2xx and (some) stm32f730xx
[2]: "OTG_FS" on stm32h7 is really just another OTG_HS peripheral, but
without any way to actually connect a HS PHY
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
When running the cdc_acm demo on a board with an external ULPI
phy, the device is unable to enumerate:
usb 1-1.8.3.1: new full-speed USB device number 51 using ehci-pci
usb 1-1.8.3.1: device descriptor read/64, error -32
usb 1-1.8.3.1: device descriptor read/64, error -32
the console shows:
[00:00:00.001,000] cdc_acm_echo: Wait for DTR
[00:00:00.007,000] usb_cdc_acm: Device suspended
[00:00:00.902,000] usb_cdc_acm: Device resumed
[00:00:00.902,000] usb_cdc_acm: from suspend
[00:00:25.526,000] usb_cdc_acm: Device suspended
By not disabling the ULPI clock in low power, the usb enumeration
is working and we can run the cdc_acm demo. While touching
this code, add some comments to clarify the macro nesting.
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Magic constants throughout the code made this difficult to reason about,
especially with two different units of measurement (bytes and words) at
play.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
The RX FIFO size is in words, so needs to be subtracted from the total
memory size *after* it's divided by 4.
Fixes#70789.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
The driver cannot handle OUT transactions for an endpoint with an
MPS smaller than 64 bytes. To solve the issue, we will not use one
fixed value, EP_MPS, but instead use the actual MPS of an endpoint,
ep_state->ep_mps.
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Like the stm32H5, stm32u5 usb device has an independent
power supply, but control bit is PWR_SVMCR_USV.
The control bit for the stm32H5 is PWR_USBSCR_USB33SV (no change)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The stm32H5 mcu has an independent USB supply to be enabled
at init with LL_PWR_EnableVDDUSB function like the stm32U5 serie.
Both series have PWR_USBSCR_USB33SV bit in their USBSCR POWER reg.
and other series all have PWR_CR2_USV bit in their CR2 POWER reg.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Isochronous endpoint issue with USB drivers on STM32G491
we setup an isochronous endpoint and are having an issue
where every other frame sends the desired data sandwiched
between garbage data.
For isochronous the parameter ep_kind into the fonction :
HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress) must be PCD_DBL_BUF.
The parameter pmaadress (EP address in The PMA) is like that:
EP address in The PMA: In case of single buffer endpoint
this parameter is 16-bit value providing the address
in PMA allocated to endpoint.
In case of double buffer endpoint this parameter
is a 32-bit value providing the endpoint buffer 0 address
in the LSB part of 32-bit value and endpoint buffer 1 address
in the MSB part of 32-bit value.
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
the FIFO Rx need to have a Minimum memory to works
distributed the rest of the ram_size memory between
the different TX FIFOs except the first which is
a control endtype with max data payload of 64 bytes
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
In order to clean up clock related code, replace static build time
clock configuration code by a runtime check.
Since I'm not able to guarantee this check will provide a correct
verdict in 100% of the cases (I'm thinking to ULPI or exotic configurations
like F7 OTG-HS), add a config option to disable it if needed.
It also doesn't apply on F1/F3 series. Keep the build time check for now.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This change doesn't consider STM32F1 series.
There are 5 categories of STM32 regarding USB domain clock:
A] USB domain clocks directly driven by CK48 clocks
B] USB domain clocks which can select either CK48 or an alternative clock
C] USB domain clocks which can select between MSI or PLL
D] USB domain clocks relying statically on a PLL output
E] USB domain clocks which can be set on 2 different PLL ouputs
For case A], there is nothing to be done. Clk48 was already configured
in a previous change (51c7643295b02ba26ddcd0fd915484114db7101c).
For case B] and C] USB domain clocks will need to be configured in
each board.
For case D] and E] relying on existing dts configuration. Though
there is no easy build time chekc that can be done.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use STM32_DT_INST_CLOCKS() to access usb device clock information.
This will help accessing domain clock information from dt nodes.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove this code to clean up the driver.
Clock activation is done from device tree configuration in clock_control
driver.
Users are informed by warning about missing configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Vbus detection is required by self-powered, with external non-USB
supply, devices to have an operational USB peripheral. The voltage
sensing, when enabled, is performed via a designated pin (PA9 is
the most common).
For greater details see section 2.6, ST application note AN4879.
Signed-off-by: Raul Pando <raul.pando@bytegrity.co.uk>
Now that USB clock prescaler is done is clock_control driver.
Remove similar part in USB driver.
Note that behavior is different: it is now up to the user to provide
the proper configuration.
Add a warning during the transition period.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Implement usb_dc_wakeup_request for STM32 USB DC and default to enable
remote wakeup functionality when the drivers is selected.
This allows the device to wake the host up by calling
usb_wakeup_request().
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
The HSI48 is enabled by clock control driver.
It is no more done by each driver that requires this clock
However when using rng or sdmmc or bluetooth/ipm or usb,
the HSI48 clock must be present in the DTS.
Add a warning for this particular check but keep the deprecated
HSI48 clock enable : keeping for legacy but to remove later.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Many device pointers are initialized at compile and never changed. This
means that the device pointer can be constified (immutable).
Automated using:
```
perl -i -pe 's/const struct device \*(?!const)(.*)= DEVICE/const struct
device *const $1= DEVICE/g' **/*.c
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Soft resetting a STM32 device currently does not reset the USB
connection, which causes a few problems: The endpoints do not respond
anymore, and within zephyr any kind of status information like
CDC_SET_CONTROL_LINE_STATE is also missing as they are not
re-negotiated.
This is fixed by stopping the USB device from zephyr side, right after
initialising the USB device.
Signed-off-by: David Jablonski <dayjaby@gmail.com>
- If the HAL headers expose the USBPRE flag, then we're probably
dealing with a F103 - using the same fundamental logic as the
code for the OTG models, set-up the USB Prescaler correctly.
- Fixes#47146
Signed-off-by: Chris Collins <chris@realsimgear.com>
On SoCs with two USB controller, Zephyr selects the FS one, and in that
case the ULPI clock needs to be disabled in sleep mode for the
controller to work.
On SoCs with a single USB HS controller, this operation is not needed.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The ULPI clock uses slightly different names on STM32H7X as those
SoC can have more than one USB controller.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
On STM32H7X SoCs, both USB controllers are HS capable, however it is not
possible to connect an ULPI PHY to the USB2 one, which limit it to FS.
Therefore the ULPI clock in sleep mode has to be disabled for USB2 in
all cases. The ULPI clock for USB1 is already disabled when needed in
the usb_dc_stm32_clock_enable() function like for other SoCs.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Do not manually enable the USB clock on STM32H7, as it is already done
in usb_dc_stm32_clock_enable() using the values in the device tree.
This partially fixes the build for STM32H7 devices with a single USB
controller.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The ULPI clock is disabled by default in run mode, there is no need to
disable it again. It is however enabled by default in sleep/low power
mode, so it needs to be disabled.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
For some reason, rather than testing for the presence of
disconnect-gpios in the devicetree, the STM32 USB Device driver was
relying on a hidden Kconfig flag to be set.
This patch removes the Kconfig option completely and simply tests for
the DT property - if it's set, you obviously know what you're doing and
obviously need the pull-up GPIO behaviour.
Signed-off-by: Chris Collins <chris@realsimgear.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
